Nonvolatile configuration cells and cell arrays

• US 6,295,230 B1
• Filed: 08/30/1999
• Issued: 09/25/2001
• Est. Priority Date: 03/14/1996
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Madurawe, Raminda U., Sansbury, James D.
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US09/385,743
• Time in Patent Office: 757 Days
• Field of Search: 365/185.28, 365/185.18, 365/185.1
• US Class Current: 365/185.28
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17772 for powering on or off
• CPC Class Codes: H03K 19/1778 Structural details for adapting physical parameters
• CPC Class Codes: H03K 19/17784 for supply voltage

Abstract

A memory cell (400) used to store data in an integrated circuit. The memory cell (400) is static, nonvolatile, and programmable. The layout of the memory cell is compact. A logic high output from the memory cell (400) is about VDD and a logic low output is about VSS. The memory cell (400) of the present invention includes a programmable memory element (515). In one embodiment, the programmable memory element (515) is coupled between supply voltage (510) and an output node (405). A pull-down device (525) is coupled between another supply voltage (505) and the output node (405). The memory cell (400) may be used to store the configuration information for a programmable logic device (121).

Claims

1. A memory cell comprising:

a tunnel dielectric;

a first voltage source;

a second voltage source, above the first voltage source during a normal operation state;

a floating gate device, coupled between the second voltage source and an output node, wherein a floating gate of the floating gate device is coupled to the tunnel dielectric;

a tunnel diode, coupled to the tunnel dielectric, wherein the tunnel dielectric transfers charge between the floating gate and the tunnel diode;

a select transistor, coupled between an erase node and the tunnel diode; and

a pull-down element, coupled between the first voltage source and the output node, wherein the pull-down element provides a first pull-down current to pull the output node to a voltage level representing a logic low when the floating gate device is programmed, and a second pull-down current that is discharged through the floating gate device to provide a voltage level representing a logic high at the output node when the floating gate device is erased.

2. The memory cell of claim 1 wherein the pull-down element is a resistor.

3. The memory cell of claim 1 wherein the pull-down element is a thin-film transistor.

4. The memory cell of claim 1 wherein the pull-down element is a polysilicon resistor.

5. The memory cell of claim 1 wherein the pull-down element has a resistance from about 100 megaohms to about 10 gigaohms.

6. The memory cell of claim 1 wherein the pull-down element has a resistance of about 1 gigaohm.

7. The memory cell of claim 1 wherein the second pull-down current is less than about 2 microamps.

8. A programmable logic integrated circuit comprising a memory cell as recited in claim 1.

9. The memory cell of claim 1 wherein the floating gate device and select transistor are n-channel transistors.

10. The memory cell of claim 1 wherein at the output node, the memory cell provides a logical high at about a level of the second voltage source and a logical low at about a level of the first voltage source.

11. The memory cell of claim 1 wherein the floating gate device is an EEPROM memory cell.

12. The memory cell of claim 1 wherein the floating gate device is a single-polysilicon EEPROM memory cell.

13. The memory cell of claim 1 wherein the memory cell is erased, the floating gate device is a double-polysilicon EEPROM memory cell.

14. The memory cell of claim 1 wherein when the memory cell is erased, the floating gate device is programmed to a high VT state.

15. The memory cell of claim 1 wherein when in a programmed state, the floating gate device has a threshold voltage from about 5 volts to about 6 volts.

16. The memory cell of claim 1 wherein when in an erased state, the floating gate device has a threshold voltage of about −

3 volts.

17. The memory cell of claim 1 wherein to store a logic low, using the memory cell, the floating gate device is a programmed state.

18. The memory cell of claim 1 wherein to store a logic high using the memory cell, the floating gate device is in an erased state.

19. The memory cell of claim 1 wherein during the normal operation state of the memory cell, a control gate node of the floating gate device is coupled to a voltage between about a VTE and about a VTP of the floating gate device.

20. The memory cell of claim 1 wherein during the normal operation state of the memory cell, a control gate node of the floating gate device is coupled to a voltage level of the second voltage source.

21. The memory cell of claim 1 wherein during a programming mode of the memory cell, a control gate node of the floating gate device is coupled to a VPP voltage, above a voltage level of the second voltage source.

22. The memory cell of claim 21 wherein during the programming mode, the erase node is grounded.

23. The memory cell of claim 21 wherein during the programming mode, the select transistor is placed in an on state.

24. The memory cell of claim 1 wherein during a programming mode of the memory cell, the select transistor is turned on my placing a voltage level of about 2 volts or greater at a gate of the select transistor.

25. The memory cell of claim 21 wherein during the programming mode, the first and second voltage sources are grounded.

26. The memory cell of claim 21 wherein during the programming mode, the second voltage source is placed at a voltage of about to VDD.

27. The memory cell of claim 26 wherein during the programming mode, the first voltage source is floating.

28. The memory cell of claim 26 wherein during the programming mode, the first voltage source is placed at a voltage of about VDD.

29. The memory cell of claim 1 wherein the floating gate device is programmed using tunneling.