Symmetric flow control for ethernet full duplex buffered repeater

• US 6,295,281 B1
• Filed: 05/16/1997
• Issued: 09/25/2001
• Est. Priority Date: 05/16/1997
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Hiscock, James S., Itkowsky, Frank A., Robins, Cary B.
• Primary Examiner(s): Olms, Douglas
• Assistant Examiner(s): PHUNKULH, BOB A
• Application Number:
  US08/857,471
• Time in Patent Office: 1,593 Days
• Field of Search: 370/229, 370/230, 370/235, 370/276, 370/277, 370/278, 370/279, 370/280, 370/282, 370/293, 370/412, 375/211, 375/213, 395/107, 395/287, 395/289, 710/292, 710/293, 710/872, 710/877
• US Class Current: 370/293
• CPC Class Codes: H04L 12/413 with random access, e.g. carrier-sense multiple-access with collision detection [CSMA-CD]
• CPC Class Codes: H04L 12/4625 Single bridge functionality, e.g. connection of two networks over a single bridge
• CPC Class Codes: H04L 47/10 Flow control; Congestion control
• CPC Class Codes: H04L 47/18 End to end
• CPC Class Codes: H04L 47/29 using a combination of thresholds

Abstract

Symmetric flow control in a buffered repeater having responsiveness to flow control frames. An Ethernet full duplex buffered repeater according to the present invention includes an internal arbitration mechanism allowing receive FIFOs of respective receive ports to transmit data over a local bus to remaining transmit ports in round-robin fashion. The transmit ports take the transmitted data off the local bus and transmit it over the respective link. Each transmit port monitors the capacity of an associated transmit FIFO, and when the available capacity falls below that required to store a maximum size frame, asserts an open collector output signal monitored by each of the ports. No port initiates transmission of a packet over the local bus when this signal is asserted. Rather than one of the transmit ports risking being unable to store a complete frame once transmission has begun, the local bus is suspended before the next frame is put on the local bus. As the receive FIFOs fill, Pause Frames are issued by the respective port over each associated link. Each port is responsive to received flow control frames for pausing transmission of data over the respective link. Each buffered repeater is cascadable with other such devices to implement an arbitrarily large buffered repeater.

Claims

1. A full duplex buffered repeater providing symmetric flow control, comprising:

a plurality of full duplex ports, each comprising respective receive and transmit queues; and

a local bus in mutual communication with each of said ports via said respective receive and transmit queues;

wherein, with respect to each of said full duplex ports, said receive queue is adapted for receiving data from an external element, for buffering said data, and for transmitting said data to said local bus for receipt by any of said transmit queues,

wherein each of said transmit queues has a threshold associated therewith and each port is operative to assert a common bus disable signal to each other of said ports when sufficient data are stored in said transmit queue to achieve said transmit queue threshold,

wherein assertion of said common bus disable signal by one of said ports disables transmission from said receive queues of all of said ports to said local bus, and

wherein each of said ports checks said bus disable signal prior to transmitting data from said respective receive queue onto said local bus, transmits said data if said bus disable signal is not asserted by any of said ports, and does not transmit said data if said disable signal is asserted by any of said ports.

2. The repeater of claim 1, wherein each of said ports further comprising circuitry for receiving an external flow control frame and for pausing transmission of data from said transmit queue in response thereto.

3. The repeater of claim 1, wherein each of said receive queues further comprises a threshold, and each of said ports further comprises circuitry for issuing a flow control frame to said external element in response to sufficient data being stored in said receive queue to achieve said receive queue threshold.

4. The repeater of claim 3, wherein said circuitry further comprises a multiplexer at an output of said transmit queue for interjecting said external flow control frame into a data stream from said transmit queue.

5. The repeater of claim 1, wherein said bus disable signal is an open-collector signal in communication with each of said ports.

6. The repeater of claim 1 further comprising a bus arbiter in communication with said ports for arbitrating between said ports an opportunity to transmit data from a respective receive queue onto said local bus.

7. The repeater of claim 1, wherein said repeater is cascadable with one or more like repeaters, wherein said local bus and said bus disable signal are common to each of said repeaters.

8. A Gigabit Ethernet full duplex buffered repeater enabling symmetric flow control, comprising:

plural full duplex ports each for connection to a respective link and comprising

a media access controller,

a receive queue for receiving data from said respective link under the control of said controller, and

a transmit queue for transmitting data to said respective link under the control of said controller; and

a local bus for receiving data from said receive queues and for transmitting said data to said transmit queues,

each of said controllers for maintaining a threshold for each of said receive and transmit queues, for issuing a flow control frame in response to said receive queue threshold being met or exceeded, for pausing transmission of data from said transmit queue when a flow control frame is received by said port over said respective link, and for disabling transmission of data to said local bus by any of said ports when said transmit queue threshold is met or exceeded.

9. The repeater of claim 8 further comprising a local bus disable signal under the control of each of said controllers for disabling transmission of data onto said local bus by any of said ports when one of said transmit queue thresholds is met or exceeded.

10. The repeater of claim 9 further comprising external connections for extending said local bus disable signal and said local bus to one or more like repeaters for forming a single cascaded repeater.

11. The repeater of claim 10 further comprising an arbiter for arbitrating local bus access between said repeaters of said cascaded repeater.

12. The repeater of claim 9, wherein each of said controllers checks said bus disable signal prior to transmitting onto said local bus, and does not transmit if said bus disable signal is asserted by any of said ports.

13. The repeater of claim 8 further comprising an open-collector bus disable signal between each of said ports and assertable by any one of said ports when said respective transmit queue threshold is met or exceeded for disabling transmission of data onto said local bus.

14. The repeater of claim 8 further comprising an arbiter for arbitrating an opportunity to transmit data onto said local bus by one of said ports.