Method and system of data transmission using differential and common mode data signaling

• US 6,295,323 B1
• Filed: 12/28/1998
• Issued: 09/25/2001
• Est. Priority Date: 12/28/1998
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Agere Systems Guardian Corp. (Broadcom, Inc.)
• Inventors: Gabara, Thaddeus J.
• Primary Examiner(s): Le, Amanda T.
• Application Number:
  US09/221,264
• Time in Patent Office: 1,002 Days
• Field of Search: 375/244, 375/257, 375/259, 375/295, 375/316
• US Class Current: 375/257
• CPC Class Codes: H04L 5/20 using different combinations of lines, e.g. phantom working

Abstract

A system and method for transferring digital data using differential and common mode data signaling is disclosed. A first digital data signal is differentially transmitted using two differential signal components sent over a two-wire interface and switched between several different discrete signal levels. A common mode signal is carried across the differential pair and used to transmit a second digital data signal. The data output stage uses a common mode injection circuit to inject a common mode voltage or current equally onto both components of the differential interface. The data receiver has a common mode extraction circuit connected to the differential interface which extracts the injected common mode signal. Common mode data transmission can be in the same or opposite direction as the differential data transmission. Common mode signals may be injected in several layers and across two or more differential interfaces to increase the data content per interface line and to improve accuracy.

Claims

1. A method of transferring digital data, comprising the steps of:

switching a first differential signal between a plurality of discrete values to communicate a first digital data signal;

switching a first common mode signal between a plurality of discrete values to communicate a second digital data signal; and

providing the first differential signal and the first common mode signal on first and second signal paths;

switching a second differential signal between a plurality of discrete values to communicate a third digital data signal;

switching a second common mode signal between a plurality of discrete value in opposition to the switched value of the first common mode signal, thereby communicating said second digital data signal as a differential signal having as differential signal components said first and second common mode signal levels; and

providing the second differential signal and the second common mode signal on third and fourth signal paths.

2. The method of claim 1, further comprising the steps of:

providing a signal value on a third signal path; and

switching the signal value on said third signal path conversely with respect to the value of said first common mode signal level, thereby communicating a second data signal as a differential signal defined by said first common mode signal value and the signal value on said third signal path.

3. The method of claim 1, further comprising the step of:

altering the magnitude of said first and second common mode signal values by a plurality of predefined amounts in response to a fourth digital data signal, said first and second common mode signal values being altered in the same manner.

4. A circuit for transmitting digital data comprising:

first and second interface nodes;

a differential switching circuit generating first and second differential signal components at said first and second interface nodes, respectively, in response to a first digital signal, the difference between laid first and second differential signal components indicating the value of said first digital signal;

a common mode injection circuit connected to said first and second interface nodes and injecting a common mode signal at said first and second interface nodes in response to a second digital signal, said injected common mode signal affecting said first and second differential signal components to substantially the same degree.

5. The circuit of claim 4, wherein said differential switching circuit comprises a current switch.

6. The circuit of claim 4, wherein said common mode injection circuit comprises a first resistance connected between said first interface node and an injection node and a second resistance connected between said injection node and said second interface node, said common mode signal being injected at said injection node.

7. The circuit of claim 4 wherein said injected common mode signal is a switched voltage having a magnitude dependent on said second digital data signal.

8. The circuit of claim 4, wherein said injected common mode signal is a switched current having a magnitude dependant on said second digital data signal.

9. A circuit for transmitting a first digital signal and for transmitting and receiving a second digital signal between first and second interface nodes, the circuit comprising:

a differential switching circuit generating first and second differential signal components at said first and second interface nodes, respectively, in response to said first digital signal, the difference between said first and second differential signal components indicating the value of said first digital signal; and

a common mode injection and extraction circuit connected to said first and second interface nodes and having transmit and receive states, when in a transmit state, said injection and extraction circuit injecting a common mode signal into said first and second differential signals in response to said second digital signal, said injection and extraction circuit extracting from said first and second differential signals a common mode signal injected onto said first and second differential signals when in a receive state, whereby said injected common mode signal affects said first and second differential signal components to substantially the same degree.

10. The circuit of claim 9, wherein said differential switching circuit comprises a current switch.

11. The circuit of claim 9, wherein said common mode injection and extraction circuit comprises:

a first resistance connected between said first interface node and a common mode access node;

a second resistance connected between said access node and said second interface node;

an injection circuit connected to said access node for injecting said common mode signal when in the transmit state and disconnected from said access node when in the receive state; and

said common mode signal being extracted from said access node.

12. In an integrated circuit, a circuit for receiving on first and second interface nodes, a first digital signal transmitted as first and second differential signal components and a second digital signal transmitted as a common mode signal carried by said differential signal components, said circuit comprising:

a differential receiver connected to said first and second interface nodes for extracting said first digital data signal; and

a common mode extraction circuit connected to said first and second interface nodes for extracting said common mode signal;

wherein;

said first digital signal is generated using differential current signaling;

said common mode extraction circuit comprises a first resistance connected between said first interface node and an extraction node and a second resistance connected between said extraction node and said second interface node, said common mode signal representing said second digital signal being extracted from said extraction node; and

said differential receiver having inputs connected to said first and second interface nodes and being differentially responsive thereto to produce an output representative of said first digital signal.

13. A circuit for receiving a first digital signal transmitted as first and second differential signal components and for receiving and transmitting a second digital signal transmitted as a common mode signal carried by said differential signal components, said circuit comprising:

an interface having first and second interface nodes receiving said first and second differential signal components;

a differential receiver connected to said first and second interface nodes and extracting said first digital data signal;

a common mode injection and extraction circuit connected to said first and second interface nodes and having transmit and receive states, said injection and extraction circuit extracting a common mode signal carried by said first and second differential signals when in a receive state, said injection and extraction circuit injecting a common mode signal into said interface in response to said second digital signal when in a transmit state, said injected common mode signal affecting said first and second differential signal components to substantially the same degree.

14. The circuit of claim 13, wherein said common mode injection and extraction circuit comprises:

a first resistance connected between said first interface node and a common mode access node;

a second resistance connected between said access node and said second interface node;

an injection circuit connected to said access node for injecting said common mode signal when in the transmit state and disconnected from said access node when in the receive state; and

said common mode signal being extracted from said access node.

15. A system for transmitting and receiving first and second digital data signals over an interface having first and second ends, said system comprising:

a differential switching circuit connected to the first end of said interface and generating first and second differential signal components in response to a first digital signal, the difference between said first and second differential signal components indicating the value of said first digital data signal;

a differential receiver connected to the second end of said interface and determining the value of said first digital data signal in accordance with the difference between received first and second differential signal components;

a common mode injection circuit connected to one of said first and second ends and injecting a common mode signal into said interface, said injected common mode signal affecting said first and second differential signal components to substantially the same degree; and

a common mode extraction circuit connected to the other of said first and a second ends for extracting said common mode signal.

16. The system of claim 15, wherein said common mode injection circuit is connected to said differential switching circuit and said common mode extraction circuit is connected to said differential receiver.

17. A circuit for transmitting first and second digital data signals over an interface comprising:

a first output stage having first and second output nodes and comprising a differential switching circuit and a common mode injection circuit;

said differential switching circuit generating first and second differential signal components in response to said first digital signal, the difference between said first and second differential signal components indicating the value of said first digital signal, said first and second differential signal components being connected to said first and second output nodes, respectively;

said common mode injection circuit being connected to said first and second output nodes and providing a common mode signal for injection into said first and second differential signals in accordance with an input signal, said injected common mode signal affecting said first and second differential signal components to substantially the same degree;

a common mode signal generator generating first and second complementary common mode signals in response to said second digital signal, said first common mode signal being provided as said input to said common mode injection circuit, said second common mode signal being connected to a third output node.

18. The circuit of claim 17, wherein said differential switching circuit comprises a current switch.

19. The circuit of claim 17, wherein said common mode injection circuit comprises a first resistance connected between said first output node and an injection node and a second resistance connected between said injection node and said second output node, said common mode signal being injected at said injection node.

20. The circuit of claim 17, wherein said common mode signal generator comprises:

a first switch connecting said first common mode signal to a first voltage when said second digital signal is high and to a second voltage when said second digital signal is low; and

a second switch connecting said second common mode signal to said first voltage when said second digital signal is low and to said second voltage when said second digital signal is high.

21. The circuit of claim 17, wherein said common mode signal generator comprises:

a second output stage generating third and fourth differential signal components in response to said second digital signal;

said third differential signal serving as said first common mode signal connected to said common mode injection circuit;

said fourth differential signal serving as said second common mode signal connected to said third output node.

22. The circuit of claim 17, wherein said interface comprises three wires aligned along a common axis, each of said wires having a substantially constant displacement from said common axis.

23. A circuit for transmitting a plurality of digital data signals comprising:

first and second output stages, each having at least two output nodes and comprising a differential switching circuit and a common mode injection circuit;

said differential switching circuit connected to said respective output nodes and generating a pair of differential signal components in response to a first and second digital signals, respectively, the difference between said differential signal components indicating the value of said respective first or second digital signal;

a common mode injection circuit connected to said respective output nodes in parallel with said differential switching circuit and injecting a common mode signal into said pair of differential signals in response to an input signal, said injected common mode signal affecting said differential signal components to substantially the same degree;

a common mode signal generator generating complementary first and second common mode signals in response to a third digital signal;

said first common mode signal being applied as the input to the common mode injection circuit in said first output stage, and said second common mode signal being applied as the input to the common mode injection circuit in said second output stage.

24. The circuit of claim 23, wherein said differential switching circuit comprises a current switch.

25. The circuit of claim 23, wherein said common mode injection circuit comprises a first resistance connected between said one of said output nodes in a respective output stage and an injection node, and a second resistance connected between said injection node and another of said output nodes in said respective output stage, said applied common mode signal being injected at said injection node.

26. The circuit of claim 23, wherein said common mode signal generator comprises:

a first switch connecting said first common mode signal to a first voltage when said third digital signal is high and to a second voltage when said third digital signal is low; and

a second switch connecting said second common mode signal to said first voltage when said third digital signal is low and to said second voltage when said third digital signal is high.

27. The circuit of claim 23 wherein said common mode signal generator comprises,

a third output stage generating a third pair of differential signal components in response to said third digital signal;

one of said third pair of differential signal components serving as said first common mode signal applied as the input to the common mode injection circuit in said first output stage;

the other of said third pair of differential signal components serving as said second common mode signal applied as the input to the common mode injection circuit in said second output stage.

28. The circuit of claim 27, wherein said third output stage generates a third common mode signal in response to a fourth data signal applied as input to the common mode injection circuit in the third output stage.

29. The circuit of claim 23, wherein said interface comprises four wires aligned along a common axis, each of said wires having a substantially constant displacement from said common axis.

30. A system for transmitting a plurality of digital data comprising:

first and second output nodes;

a first differential switching circuit connected to said first and second output nodes, said first differential switching circuit connecting said first output to a first current source and said second output to a first current sink in a first differential output state and connecting said first output to said first current sink and said second output to said first current source in a second differential output state;

a first common mode switching circuit connected to said first and second output nodes, said first common mode switching circuit connecting said first and second output nodes to a second current source in a first common mode output state and connecting said first and second output nodes to a second current sink in a second common mode output state;

a third output node;

a second common mode switching circuit connected to said third output node, said second common mode switching circuit connecting said third output node to said second current sink in said first common mode output state and connecting said third output node to said second current source in said second common mode output state;

a common current node;

a first resistance connected between said first output node and said common current node;

a second resistance connected between said common current node and said second output node;

said common current node being electrically connected to said third output node.

31. The system of claim 30, further comprising:

a fourth output node;

said second common mode switching circuit being connected to said third output node and connecting said fourth output node to said second current sink in said first common mode output state and connecting said fourth output node to said second current source in said second common mode output state;

a third resistance connecting said common current node to said third output node; and

a fourth resistance connecting said common current node to said fourth output node.