Method and apparatus for eliminating the transpose buffer during a decomposed forward or inverse 2-dimensional discrete cosine transform through operand decomposition, storage and retrieval
First Claim
1. A computer system including a processor for performing matrix transform operations, comprising:
- a single-ported RAM memory having memory cell locations for storing operands, said processor operable to store operands at memory cell locations of said RAM memory selected to permit retrieval of said operands in a desired sequence and collision free retrieval by said processor of pairs of said operands from identified ones of said memory cell locations during a single memory cycle, said processor further being operable to perform a matrix transform operation on said pair of retrieved operands to produce transformed values of said operands, and then to store said transformed values at the same memory cell locations at which the operands of said retrieved pair of operands were stored.
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Abstract
A method and apparatus is presented for video image compression using a unique operand decomposition technique combined with an innovative data scatter and retrieve process. This combination of features allows the use of single ported RAM structures where multiported RAMS would normally be used, such as when retrieving two operands in the same time cycle. As applied to the Discrete Cosine Transformation this method and appatatus additionally allows elimination of the usual prior art use of a separate transpose matrix buffer. The elimination of the separate transpose matrix buffer is accomplished by combining the transpose matrix intermediate results memory storage with the memory buffer used for the other intermediate results in a double buffer system. The double buffer memory locations are chosen so that the intermediate storage register address are orthogonal to the initial source addresses, thereby using one of the properties of the Discrete Cosine Transform to improve speed of operation and reduce the circuit area and system cost.
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Citations
4 Claims
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1. A computer system including a processor for performing matrix transform operations, comprising:
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a single-ported RAM memory having memory cell locations for storing operands, said processor operable to store operands at memory cell locations of said RAM memory selected to permit retrieval of said operands in a desired sequence and collision free retrieval by said processor of pairs of said operands from identified ones of said memory cell locations during a single memory cycle, said processor further being operable to perform a matrix transform operation on said pair of retrieved operands to produce transformed values of said operands, and then to store said transformed values at the same memory cell locations at which the operands of said retrieved pair of operands were stored. - View Dependent Claims (2)
a discrete cosine transformation circuit, a quantization transformation circuit, and wherein said single ported RAM structure comprises a single double buffer memory element logically connected between said discrete cosine transformation circuit and said quantization transformation circuit, wherein said single double buffer memory element is the only buffer memory element.
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3. A method for video signal compression and decompression, comprising:
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receiving a video signal comprised of data elements;
performing at least one of a discrete cosine transform operation and a quantization transform operation on said video signal utilizing a processor and a single double buffer memory element, wherein said performing step further includes the steps of, storing said data elements in said double buffer memory element, said double buffer memory element being comprised of single ported RAM cells, said storing step further comprising the steps of, storing an initial operand in each of said single ported RAM cells via the use of a specific ordering of said initial operands in said buffer, retrieving a pair of said initial operands from said double buffer memory in a single memory cycle, said processor performing at least one of said discrete cosine transform operation and said quantization transform operation on said pair of said initial operands to produce an intermediate transformed value of each of said initial operands, storing in the same ones of said single ported RAM cells said intermediate transformed values of said initial operands, and said processor performing said discrete cosine transform and said quantization transform to generate at least one of a compressed video signal and a decompressed video signal.
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4. A method for video signal decompression, comprising:
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receiving a compressed video signal comprised of data elements;
performing by a data processor at least one of an inverse discrete cosine transform operation and an inverse quantization transform operation on said video signal utilizing a single double buffer memory element, wherein said performing step further includes the steps of, storing said data elements in said double buffer memory element, said double buffer memory element being comprised of single ported RAM cells, said storing step further comprising the steps of, storing an initial operand in each of said single ported RAM cells via the use of a specific ordering of said initial operands in said buffer, retrieving a pair of said initial operands from said double buffer memory in a single memory cycle, said data processor performing at least one of said inverse discrete cosine transform operation and said inverse quantization transform operation said pair of said initial operands, storing in the same ones of said single ported RAM cells said intermediate transformed values of said initial operands, and said data processor performing said inverse discrete cosine transform and said inverse quantization transform to generate a decompressed video signal.
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Specification