Method of processing memory requests in a pipelined memory controller

• US 6,295,592 B1
• Filed: 07/31/1998
• Issued: 09/25/2001
• Est. Priority Date: 07/31/1998
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joseph
• Primary Examiner(s): Bragdon, Reginald G.
• Assistant Examiner(s): Anderson, Matthew D.
• Application Number:
  US09/127,282
• Time in Patent Office: 1,152 Days
• Field of Search: 711/169, 711/105, 711/160, 711/167, 711/168, 395/670, 712/215
• US Class Current: 711/169
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure

Abstract

A method for processing multiple memory requests in a pipeline. Each memory request is processed in part by a plurality of stages. In a first stage, the memory request is decoded. In a second stage, the address information for the memory request is processed. In a third stage, the data for the memory request is transferred. A request buffer is used to hold each of the memory requests during the processing of each of the memory requests.

Claims

1. A method of processing at least one memory request, comprising:

processing the at least one memory request in a plurality of stages, wherein in a first stage, the at least one memory request is received from a memory requester and stored in a request buffer, wherein in a second stage the at least one memory request is decoded, wherein in a third stage the at least one memory request is sent to a memory module, and wherein in a fourth stage the data from the at least one memory request is communicated from the memory module to a data transfer module.

2. The method as defined in claim 1, wherein during the act of processing, each of the first, second and third stages are executed during an identical number of clock cycles.

3. The method as defined in claim 1, wherein during the act of processing, each of the first, second and third stages are executed independently.

4. The method as defined in claim 1, wherein during the act of processing, each of the first, second and third stages are executed in parallel.

5. The method as defined in claim 1, wherein the act of processing includes the act of storing the first and second memory requests in at least one rotational register contained in the request buffer.

6. The method as defined in claim 5, further comprising the act of assigning a decode pointer, an address pointer, and a data pointer to reference the register of the memory request that is being processed by the decode module, the address module and the data module, respectively.

7. The method as defined in claim 1, wherein the act of processing further includes the act of determining what type of memory is being requested by the memory request.

8. The method as defined in claim 1, wherein the act of processing further comprises the act of determining which data bank of the memory module contains the data for the memory request.

9. The method as defined in claim 1, wherein the act of processing further comprises the act of determining an error correction method.

10. The method as defined in claim 1, wherein the act of processing further comprises the act of sending the row and column address of the memory request to the memory module.

11. A method of manufacturing a pipelined memory controller, comprising:

connecting a request queue having a plurality of registers to a state machine;

assigning a request pointer to reference the most recent memory request in the request queue; and

coupling a data transfer module, a decode module and a memory address module to the state machine, each of the modules having a pointer which points to a memory request in the request queue.

12. A method of pipelining memory requests in a memory controller, comprising:

receiving a memory request from a processor;

storing the memory request in a first register;

pointing a request pointer to the first register;

pointing a decode pointer to the first register;

pointing an address pointer to the first register;

decoding the address of the memory request in the first register;

sending the address of the memory request to a memory module;

receiving a second memory request;

storing the second memory request in a second register;

updating the request pointer to reference the second memory request;

updating the decode pointer to reference the second memory request;

updating the address pointer to reference the second memory request;

decoding the address in the second memory address;

incrementing the decode and address pointers;

sending the address of the memory request to a memory module; and

transferring the data requested by the first and second memory requests from the memory module to a data transfer module.

13. The method as defined in claim 12, further comprising the act of updating the decode pointer, the address pointer and the data pointer by a state machine at the beginning of each stage in a pipeline.

14. The method as defined in claim 12, wherein the act of transferring the data further includes the act of supplying a clock signal to a memory module.

15. The method as defined in claim 12, wherein each of the acts of storing further includes the act of storing the first and second memory requests in at least one rotational register.

16. The method as defined in claim 12, wherein each of the acts of decoding further includes the act of determining what type of memory is being requested by the memory request.

17. The method as defined in claim 12, wherein each of the acts of decoding further includes the act of determining which data bank of the memory module contains the data for the memory request.

18. The method as defined in claim 12, wherein each of the acts of decoding further includes the act of determining an error correction method.