Method and apparatus for the automated design of memory devices

• US 6,295,627 B1
• Filed: 04/02/1999
• Issued: 09/25/2001
• Est. Priority Date: 12/04/1998
• Status: Expired due to Fees

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Gowni, Shiva P., Patel, Alpesh B., Wang, Bo B.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): DO, THUAN V
• Application Number:
  US09/285,510
• Time in Patent Office: 907 Days
• Field of Search: 716/4, 716/1
• US Class Current: 716/104
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

A design, layout, schematic, netlist, abstract or other equivalent circuit representations for a memory that may have redundant circuitry may be generated from a set of user inputs acquired through a graphical user interface. Based on the user inputs one or more leaf cells is/are generated. Then using the leaf cells, a design database for the layout is generated from the user inputs. The design database reflects physical hierarchies of the layout and may include redundancy circuitry within a data and/or address path, parallel to a non-redundant data and/or address path within the layout. The above-mentioned parameters described by the user inputs may include an array size, a defect rate, and/or a leaf cell design, layout or schematic. This scheme may be embodied as a set of computer-readable instructions, for example to be executed by a computer system. The user may rearrange the memory array architecture by changing a parameter selected from the group consisting of array size, defect rate, line width, line spacing, line length, gate width, transistor spacing, gate length, transistor length, resistivity, capacitance, and other physical and/or electrical device parameters.

Claims

1. A computer implemented method for generating a netlist for a memory comprising:

a) acquiring a set of user inputs describing parameters of the netlist through a graphical user interface, wherein the parameters comprise an array size, a defect rate, and a leaf cell design and wherein the memory comprises redundant circuitry comprising redundant data paths and redundant address paths for redundant columns;

b) generating one or more leaf cells from a subset of the user inputs; and

c) automatically generating, from the leaf cells, a design database for the netlist from the user inputs, wherein the design database reflects physical hierarchies of the netlist, and wherein the step of automatically generating further comprises the steps of;

i) automatically generating redundant circuitry when the memory contains at least 256 K bits, and ii) automatically generating redundant circuitry when a user input has met a predetermined value.

2. A computer implemented method for generating a peripheral circuit netlist, including redundancy logic, comprising:

a) acquiring a set of user inputs describing parameters of the peripheral circuit netlist through a graphical user interface, wherein the parameters comprise line width, line spacing, line length, gate width, transistor spacing, resistivity, and capacitance, and wherein the peripheral circuit netlist is for redundant circuitry comprising redundant data paths and redundant address paths for redundant columns;

b) generating one or more leaf cells from a subset of the user inputs;

c) automatically synthesizing variations of physical device hierarchies for the peripheral circuitry based on parameters of the leaf cells; and

d) automatically generating, from the leaf cells and the variations of physical device hierarchies, a design database for the peripheral circuit netlist, and wherein the step of automatically generating further comprises the step of automatically generating redundant circuitry when a user input has met a predetermined value.

3. An advanced graphical interface configured to allow a user to rearrange a memory array architecture by performing the steps of:

acquiring a set of user inputs describing parameters of the memory array architecture through a graphical user interface, wherein the parameters comprise an array size, a defect rate, and a leaf cell design and wherein the memory array architecture comprises redundant circuitry comprising redundant data paths and redundant address paths for redundant columns;

generating leaf cells from a subset of the user inputs;

automatically generating, from the leaf cells, a design database for the memory array architecture from the user inputs, wherein the design database reflects physical hierarchies of the memory array architecture, and wherein the step of automatically generating further comprises the steps of automatically generating redundant circuitry when the memory array architecture contains at least 256 K bits, and automatically generating redundant circuitry when a user input has met a predetermined value;

accepting user selection of at least one leaf cell; and

automatically generating, from the selected leaf cells, a rearranged memory array architecture.

4. A computer implemented method of generating a netlist for an integrated circuit having a plurality of non-redundant circuits and at least one redundant circuit, comprising:

a) acquiring a set of user inputs describing parameters of the netlist through a graphical user interface;

b) generating one or more leaf cells from a subset of the user inputs; and

c) automatically generating, from the leaf cells, a design database for the netlist from the user inputs, wherein the step of automatically generating further comprises the step of automatically generating redundant circuitry when a user input has met a predetermined value such that the design database includes the redundant circuitry and reflects physical hierarchies of the netlist, and wherein each redundant circuit is combined in a parallel circuit fashion with the non-redundant circuits to comprise an input path, a functional circuit, and an output path, and wherein the redundant circuitry comprises redundant data paths and redundant address paths for redundant columns.