Method of fabrication of a microstructure having an internal cavity

• US 6,297,072 B1
• Filed: 04/16/1999
• Issued: 10/02/2001
• Est. Priority Date: 04/17/1998
• Status: Active Grant

• Current Assignee: Cp Clare, Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Original Assignee: Interuniversitair Micro-Electronica Centrum VZW (IMEC International)
• Inventors: Tilmans, Hendrikus A. C., Beyne, Eric, Van de Peer, Myriam
• Primary Examiner(s): Everhart, Caridad
• Application Number:
  US09/293,750
• Time in Patent Office: 900 Days
• Field of Search: 438/25, 438/26, 438/433, 438/434, 438/456, 438/106, 438/422, 438/421, 438/411
• US Class Current: 438/106
• CPC Class Codes: B81B 7/0077 Other packages not provided for in groups B81B7/0035 - B81B7/0074
• CPC Class Codes: B81C 1/00293 maintaining a controlled atmosphere with processes not provided for in B81C1/00285
• CPC Class Codes: G01J 5/045 Sealings; Vacuum enclosures; Encapsulated packages; Wafer bonding structures; Getter arrangements getter arrangements per se H01L23/26 and H01L21/3221
• CPC Class Codes: G01L 9/0042 Constructional details associated with semiconductive diaphragm sensors, e.g. etching, or constructional details of non-semiconductive diaphragms details about the integration or bonding of piezoresistor in or on the diaphragm G01L9/0052 and G01L9/0057 respectively
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: H01H 1/0036 Switches making use of microelectromechanical systems [MEMS] for electromagnetic relays H01H50/005; for electrostatic relays H01H59/0009
• CPC Class Codes: H01H 35/14 Switches operated by change of acceleration, e.g. by shock or vibration, inertia switch wherein the liquid constitutes a contact of the switch H01H29/002
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01025 Manganese [Mn]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H03H 9/1057 for microelectro-mechanical devices

Abstract

A method of fabricating a microstructure having an inside cavity. The method includes depositing a first layer or a first stack of layers in a substantially closed geometric configuration on a first substrate. Then, performing an indent on the first layer or on the top layer of said first stack of layers. Then, depositing a second layer or a second stack of layers substantially with said substantially closed geometric configuration on a second substrate. Then, aligning and bonding said first substrate on said second substrate such that a microstructure having a cavity is formed according to said closed geometry configuration.

Claims

1. A method of fabricating a microstructure having an inside cavity comprising:

making at least a first layer in a substantially closed geometric configuration on a first substrate, said substantially closed geometric configuration defining a cavity therein;

creating an indent in said first layer;

making at least a second layer substantially with said substantially closed geometric configuration on a second substrate; and

aligning and bonding said first substrate on said second substrate such that a microstructure is formed with said cavity formed within said closed geometric configuration.

2. The method as recited in claim 1, wherein the indent is created by using photolithographic and/or chemical acts.

3. The method as recited in claim 1, wherein the indent is created by removing a part of said first layer using a shearing tool.

4. The method as recited in claim 1, wherein the indent is created by applying a force with an indent tool on said first layer.

5. The method as recited in claim 1, wherein a pre-treatment prior to the aligning and bonding of said substrates is performed on both substrates, said pre-treatment including a plasma etching treatment.

6. The method as recited in claim 1, wherein a pre-bonding treatment is performed after the alignment of both substrates in order to form the microstructure.

7. The method as recited in claim 6, wherein the pre-bonding treatment comprises in heating the microstructure to a temperature well below the melting temperature of said first layer.

8. The method as recited in claim 1, wherein said first layer includes a solder layer essentially made of PbSn.

9. The method as recited in claim 1, wherein the first layer comprises a metallization seed layer.

10. The method as recited in claim 1, further comprising pumping said cavity to a predetermined pressure prior to and/or while executing the bonding.

11. The method as recited in claim 1, further comprising the step of filling the cavity with a gas or a gas mixture to a predetermined pressure prior to and/or while executing the bonding.

12. The method as recited in claim 11, wherein the gas is an inert gas.

13. The method as recited claim 1, wherein the indent is closed by reflowing the first layer at a reflow temperature above or equal to or just below the melting temperature of said first layer.

14. The method as recited in claim 13, wherein the reflowing is performed in a vacuum environment.

15. The method as recited in claim 14, wherein the reflowing is performed in an inert gas environment.

16. The method as recited in claim 1, wherein the reflowing is performed at a temperature which is less than the melting point of the substrates and the other structures thereon excluded of said first layer.

17. The method as recited in claim 1, wherein both substrates can be silicon or chips in silicon wafers or one substrate being a chip, the other substrate a wafer.

18. The method as recited in claim 1, wherein a window is made in one of the two substrates in order to let electromagnetic radiation to enter the cavity.

19. The method as recited in claim 1, wherein one of said substrates is transparent to electromagnetic radiation such that the radiation can enter the cavity.

20. The method, as recited in claim 1, wherein a microreed switch, a capacitive microaccelerator, a vacuum microtriode, a microresonator, a microrelay and a microswitch are realized.

21. A method of fabricating a microstructure having an inside cavity comprising:

making at least a first stack of layers in a substantially closed geometric configuration on a first substrate thereby defining a cavity within said substantially closed geometric configuration;

creating an indent on the top layer of said first stack of layers;

making at least a second stack of layers substantially with said substantially closed geometric configuration on a second substrate; and

aligning and bonding said first substrate on said second substrate such that a microstructure is formed with said cavity within said closed geometric configuration.

22. The method as recited in claim 21, wherein the indent is created by using photolithographic and/or chemical acts.

23. The method as recited in claim 21, wherein the indent is created by removing a part of at least one of the layers of the first stack of layers using a shearing tool.

24. The method as recited in claim 21, wherein the indent is created by applying a force with an indent tool on at least one of the layers of the first stack of layers.

25. The method as recited in claim 21, wherein a pre-treatment prior to the aligning and bonding of said substrates is performed on both substrates, said pre-treatment including a plasma etching treatment.

26. The method as recited in claim 21, wherein a pre-bonding treatment is performed after the alignment of both substrates in order to form the microstructure.

27. The method as recited in claim 26, wherein the pre-bonding treatment comprises in heating the microstructure to a temperature well below the melting temperature of at least one of the layers of the first stack of layers.

28. The method as recited in claim 21, wherein said first stack of layers includes a solder layer essentially made of PbSn.

29. The method as recited in claim 21, wherein the first stack of layers comprises a metallization seed layer.

30. The method as recited in claim 21, further comprising pumping said cavity to a predetermined pressure prior to and/or while executing the bonding.

31. The method as recited in claim 21, further comprising filling the cavity with a gas or a gas mixture to a predetermined pressure prior to and/or while executing the bonding.

32. The method as recited in claim 31, wherein the gas is an inert gas.

33. The method as recited claim 21, wherein the indent is closed by reflowing the top layer of the first stack of layers at a reflow temperature above or equal to or just below the melting temperature of at least one of the layers of said first stack of layers.

34. The method as recited in claim 33, wherein the reflowing is performed in a vacuum environment.

35. The method as recited in claim 34, wherein the reflowing is performed in an inert gas environment.

36. The method as recited in claim 21, wherein the reflowing is performed at a temperature which is less than the melting point of the substrates and the other structures thereon excluded at least one of the layers of said first stack of layers.

37. The method as recited in claim 21, wherein both substrates can be silicon or chips in silicon wafers or one substrate being a chip, the other substrate a wafer.

38. The method as recited in claim 21, wherein a window is made in one of the two substrates in order to let electromagnetic radiation to enter the cavity.

39. The method as recited in claim 21, wherein one of said substrates is transparent to electromagnetic radiation such that the radiation can enter the cavity.

40. The method, as recited in claim 21 wherein a microreed switch, a capacitive microaccelerator, a vacuum microtriode, a microresonator, a microrelay and a microswitch are realised.

41. A method of fabricating a microstructure having an inside cavity comprising;

making at least a first stack of layers including a solder layer essentially made of PbSn in a substantially closed geometric, configuration on a first substrate, thereby defining a cavity;

creating an indent on the top layer of said first stack of layers;

making at least a second stack of layers substantially with said substantially closed geometric configuration on a second substrate; and

aligning and bonding said first substrate on said second substrate such that a microstructure is formed with said cavity formed within said closed geometric configuration.

42. A method of fabricating a microstructure having an inside cavity, the method comprising:

forming at least a first layer in a substantially closed geometric configuration on a first substrate thereby defining a cavity within said substantially closed geometric configuration, wherein said first layer includes a solder layer essentially made of PbSn;

creating an indent in said first layer;

making at least a second layer substantially with said substantially closed geometric configuration on a second substrate; and

aligning and bonding said first substrate on said second substrate such that a microstructure is formed with said cavity formed within said closed geometric configuration.