Tilt-angle ion implant to improve junction breakdown in flash memory application

• US 6,297,098 B1
• Filed: 11/01/1999
• Issued: 10/02/2001
• Est. Priority Date: 11/01/1999
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chrong-Jung, Chu, Wen-Ting, Su, Hung-Der, Chen, Jong
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US09/431,236
• Time in Patent Office: 701 Days
• Field of Search: 438/257, 438/264, 438/302, 438/525, 438/529
• US Class Current: 438/264
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H10B 41/30 characterised by the memory core region

Abstract

A method is disclosed for forming LDDs (Lightly Doped Drains) in high voltage devices employed in non-volatile memories and DDDs (Doubly Doped Drains) in flash memory applications. The high voltage device is formed by using two successive ion implantations at a tilted angle which provides an improved gradation of doped profile near the junction and the attendant improvement in junction breakdown at higher voltages. The doubly doped drain in a stacked flash memory cell is also formed by two implantations, but at an optimum tilt-angle, where the first implantation is lightly doped, and the second, heavily doped. The resulting DDD provides faster program speed, reduced program current, increase read current and reduced drain disturb in the flash memory cell.

Claims

1. An optimum implant angle method of forming a DDD (Doubly Doped Drain) in a stacked flash memory cell comprising the steps of:

providing a silicon substrate having a plurality of active and field regions defined;

forming a gate oxide layer over said substrate;

forming a floating gate over said thick gate oxide layer;

forming an inter-gate oxide layer over said floating gate;

forming a stacked control gate over said inter-gate oxide;

forming oxide spacers on sidewalls of said stacked gate;

performing a first lightly doped implantation with an optimum tilt-angle between about 40 to 50 degrees once from the right and once from the left with respect to the sidewalls of said stacked gate; and

then

performing a second heavily doped implantation with said optimum tilt-angle once from the right and once from the left with respect to the sidewalls of said stacked gate.

2. The method of claim 1, wherein said gate oxide layer has a thickness between about 80 to 95 Å

.

3. The method of claim 1, wherein said forming said floating gate is accomplished by depositing a first polysilicon layer to a thickness between about 1000 to 2000 Å

, and then etching said first polysilicon layer.

4. The method of claim 1, wherein said forming said inter-gate oxide layer over said floating gate is accomplished by growing an oxide layer at temperature between about 570 to 625°

C.

5. The method of claim 1, wherein said inter-gate oxide layer has a thickness between about 120 to 160 Å

.

6. The method of claim 1, wherein said forming said stacked control gate is accomplished by depositing a second polysilicon layer to a thickness between about 1500 to 2000 Å

, and then etching said second polysilicon layer.

7. The method of claim 1, wherein said forming said oxide spacers on sidewalls of said stacked gate is accomplished by depositing an oxide layer to a thickness between about 1200 to 1500 Å

, and then anisotropically etching said oxide layer.

8. The method of claim 1, wherein said performing said first lightly doped implantation is accomplished with phosphorous ions at a dosage level between about 1×

10¹³ to 5×

10¹³ atoms/cm², and at energy level between about 35 to 55 KeV.

9. The method of claim 1, wherein said performing said second lightly doped implantation is accomplished with arsenic ions at a dosage level between about 2×

10¹⁵ to 5×

10¹⁵ atoms/cm², and at energy level between about 40 to 60 KeV.

10. An optimum implant angle method of forming a DDD (Doubly Doped Drain) in a flash memory cell comprising the steps of:

providing a substrate having active and passive regions defined;

forming a plurality of gates over said substrate;

performing a first lightly doped implantation with an optimum tilt-angle to form a junction of said DDD in said flash memory cell, wherein said first lightly doped implantation is performed twice, once from the right and once from the left with an optimum tilt-angle between about 40 to 50 degrees with respect to the sidewalls of said flash memory cell;

then

performing a second heavily doped implantation with said optimum tilt-angle to form a surface region of said DDD in said flash memory cell, wherein said second heavily doped implantation is performed twice, once from the right and once from the left with said optimum tilt-angle with respect to the sidewalls of said flash memory cell;

or, alternatively

rotating said substrate at said optimum tilt-angle while performing said first lightly doped implantation, and then said second heavily implantation; and

performing a drive-in diffusion of said doubly doped drain, DDD.

11. The method of claim 10, wherein said plurality of gates are floating gate and control gate of said flash memory cell.

12. The method of claim 10, wherein said performing said first lightly doped implantation is accomplished with phosphorous ions at a dosage level between about 1×

10¹³ to 5×

10¹³ atoms/cm², and at energy level between about 35 to 55 KeV.

13. The method of claim 10, wherein said performing said second heavily doped implantation is accomplished with arsenic ions at a dosage level between about 2×

10¹⁵ to 5×

10¹⁵ atoms/cm² at energy level between about 40 to 60 KeV.

14. The method of claim 10, wherein said performing said drive-in diffusion of said DDD is accomplished at a temperature between about 850 to 950°

C.