Method for producing an MOS transistor structure with elevated body conductivity

• US 6,297,101 B1
• Filed: 02/29/2000
• Issued: 10/02/2001
• Est. Priority Date: 03/01/1999
• Status: Expired due to Term

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Schaeffer, Carsten
• Primary Examiner(s): Zarabian, Amir
• Assistant Examiner(s): Wilson, Christian D.
• Application Number:
  US09/515,088
• Time in Patent Office: 581 Days
• Field of Search: 438/133, 438/135, 438/138, 438/142, 438/206, 438/209, 438/212, 438/268, 438/270, 438/919, 438/524, 438/525
• US Class Current: 438/268
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: Y10S 438/919 Compensation doping

Abstract

In a method is described for producing an MOS transistor structure with elevated body conductivity, a substrate layer is prepared and body regions are formed therein the body regions defining a main surface of the transistor structure and at least one channel region is also formed. Gate oxide and gate electrodes are formed in the region of the main surface, and source regions are formed that extend from the main surface into the body regions. An implantation of dopant of a first conductivity type occurs in at least a part of the channel region, this implantation dosage being controlled such that a re-doping of the body region into an area of the first conductivity type does not occur in the implantation region.

Claims

1. A method for producing an MOS transistor structure, comprising the steps of:

providing a substrate layer of a first conductivity type;

forming a body region of a second conductivity type adjoining said substrate layer, said body region of a second conductivity defining a primary surface;

forming source regions of said first conductivity type at said primary surface and extending into said body region and thereby defining at least one channel region between two of said source regions and said substrate layer;

forming a gate trench in said channel region proceeding from said primary surface to said substrate layer, said gate trench having a sidewall;

obliquely implanting dopant of said first conductivity type into said channel region to dope at least an upper portion of said sidewall of said gate trench, and using an implantation dosage so that substantially no redoping of said body region, other than at said upper portion of said sidewall, into said first conductivity type occurs, other than at said upper portion of said sidewall, and said body region retains said second conductivity type; and

forming a gate oxide and a gate electrode in said gate trench.

2. A method as claimed in claim 1 wherein said primary surface has a surface normal, and comprising obliquely implanting said dopant of said first conductivity type at an angle in a range between 20°

and 60°

to said surface normal.

3. A method as claimed in claim 1 comprising dividing said body region of said second conductivity type into a plurality of discrete body regions by forming a plurality of gate trenches in said body region of said conductivity type.

4. A method as claimed in claim 1 comprising implanting doping material of said first conductivity type by implantation onto said primary surface, and forming said gate oxide and said gate electrodes on said primary surface to adjoin at least one of said body regions and one source region.

5. A method as claimed in claim 1 comprising forming a layer of said second conductivity type on a surface of said substrate layer which is opposite to said primary surface.