Structure and method for dual gate oxide thicknesses

• US 6,297,103 B1
• Filed: 02/28/2000
• Issued: 10/02/2001
• Est. Priority Date: 02/28/2000
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ahn, Kie Y., Forbes, Leonard
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Dang, Phuc T.
• Application Number:
  US09/514,629
• Time in Patent Office: 582 Days
• Field of Search: 438/239, 438/275, 438/279, 438/294, 438/351, 438/261, 438/283, 438/597, 257/36, 257/52, 257/298, 257/315
• US Class Current: 438/275
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants

Abstract

Structures and methods involving at least a pair of gate oxides having different thicknesses, one suitable for use in a logic device and one suitable for use in a memory device, have been shown. The method provided by the present invention affords a technique for ultra thin dual gate oxides having different thicknesses using a low temperature process in which no etching steps are required. The method includes forming a pair of gate oxides to a first thickness, which in one embodiment, includes a thickness of less than 5 nanometers. In one embodiment, forming the pair of gate oxides includes using a low-temperature oxidation method. A thin dielectric layer is then formed on one of the pair of gate oxides which is to remain as a thin gate oxide region for a transistor for use in a logic device. The thin dielectric layer exhibits a high resistance to oxidation at high temperatures. In one embodiment, the thin dielectric layer includes a thin dielectric layer of silicon nitride (Si₃N₄) formed using jet vapor deposition (JVD). The other of the pair of gate oxides is then formed to a second thickness to serve as a thick gate oxide region for a transistor for use in a memory device. Another embodiment of the present invention includes the structure of a logic device and a memory device formed on a single substrate as well as systems formed according to the method described above. In one embodiment, a dielectric layer of the transistor for use in the logic device has a thickness of less than 7 nanometers and a dielectric layer in the transistor for use in the memory device has a thickness of less than 12 nanometers.

Claims

1. A method for fabricating a circuit having logic and memory devices on a single substrate, comprising:

forming a number of transistors on the substrate, wherein forming the number of transistors includes forming a first transistor for use in the logic device and forming a second transistor for use in the memory device on the substrate, and wherein forming the first transistor and the second transistor includes;

forming a pair of gate oxides to a first thickness on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers (nm) by atomic oxygen generated in high-density krypton plasma at approximately 400 degrees Celsius;

forming a thin dielectric layer on one of the pair of gate oxides, wherein the thin dielectric layer exhibits a high resistance to oxidation at high temperatures; and

forming the other of the pair of gate oxides to a second thickness; and

wiring the logic device and the memory device together using a metallization process to implement a specific circuit function.

2. The method of claim 1, wherein forming the pair of gate oxides to a first thickness includes a first thickness suitable for the operation of the logic device.

3. The method of claim 1, wherein forming a thin dielectric layer on one of the pair of gate oxides includes forming a thin dielectric layer of silicon nitride (Si₃N₄) to a thickness of less than 3 nanometers (nm) using jet vapor deposition (JVD) for use in the logic device.

4. A method for fabricating a circuit having logic and memory devices on a single substrate, comprising:

forming a number of transistors on the substrate, wherein forming the number of transistors includes forming at least one transistor for use in the logic device and forming at least one transistor for use in the memory device on the substrate, and wherein forming the first and the second transistors includes;

forming a pair of gate oxides to a first thickness suitable for the operation of the logic device on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers (nm) by atomic oxygen generated in high-density krypton plasma at approximately 400 degrees Celsius;

forming a thin dielectric layer on one of the pair of gate oxides, wherein the thin dielectric layer exhibits a high resistance to boron penetration at high temperatures; and

forming the other of the pair of gate oxides to a second thickness; and

wiring the logic device to the memory device using a metallization process to implement a specific circuit function.

5. The method of claim 4, wherein forming a thin dielectric layer on one of the pair of gate oxides includes forming a thin dielectric layer of silicon nitride (Si₃N₄) to a thickness of less than 3 nanometers using jet vapor deposition (JVD) for use in the logic device.

6. The method of claim 5, wherein forming a thin dielectric layer on one of the pair of gate oxides for use in the logic device is performed before forming the other of the pair of gate oxides to a second thickness.

7. The method of claim 4, wherein forming a thin dielectric layer on one of the pair of gate oxides includes forming a thin dielectric layer which exhibits a strong resistance to the formation of an interfacial oxide layer when forming the other of the pair of gate oxides to a second thickness.

8. The method of claim 7, wherein forming the other of the pair of gate oxides to a second thickness includes forming the other of the pair of gate oxides to a second thickness of less than 10 nanometers including the first thickness, which has not been etched, by a process using atomic oxygen generated in high-density krypton plasma at approximately 400 degrees Celsius for use in the memory device.

9. The method of claim 8, wherein the method of forming the first and the second transistors further includes forming a boron doped polysilicon gate on the thin dielectric layer as part of the first transistor and on the other gate oxide as part of the second transistor.

10. A method for fabricating a circuit having logic and memory devices on a single substrate, comprising:

forming a number of transistors on the substrate, wherein forming the number of transistors includes forming at least one transistor for use in a logic device and forming at least one transistor for use in a memory device on the substrate, and wherein forming the first transistor and the second transistor includes;

forming a pair of gate oxides to a first thickness on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides by atomic oxygen generated in high-density krypton plasma at approximately 400 degrees Celsius;

forming a thin layer of silicon nitride (Si₃N₄) on one of the pair of gate oxides using jet vapor deposition (JVD); and

forming the other of the pair of gate oxides to a second thickness; and

;

wiring the logic device to the memory device using a metallization process to implement a specific circuit function.

11. The method of claim 10, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness suitable for use in the logic device using a low-temperature oxidation method.

12. The method of claim 11, wherein forming the pair of gate oxides to a first thickness suitable for use in the logic device includes forming the pair of gate oxides to a first thickness of less than 5 nanometers.

13. The method of claim 10, wherein forming a thin layer of silicon nitride (Si₃N₄) on one of the pair of gate oxides using jet vapor deposition (JVD) includes forming a thin layer of silicon nitride (Si₃N₄) on one of the pair of gate oxides for use in the logic device.

14. The method of claim 13, wherein forming a thin layer of silicon nitride (Si₃N₄) on one of the pair of gate oxides for use in the logic device includes forming the thin layer of Si₃N₄ to have a thickness of less than 3 nanometers.

15. A method for fabricating a circuit having logic and memory devices on a single substrate, comprising:

forming a number of transistors on the substrate, wherein forming the number of transistors includes forming at least one transistor for use in a logic device and forming at least one transistor for use in a memory device on the substrate, and wherein forming the first transistor and the second transistor includes;

forming a pair of gate oxides to a first thickness on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers (nm) by atomic oxygen generated in high-density krypton plasma at approximately 400 degrees Celsius;

forming a thin layer of silicon nitride (Si₃N₄) on one of the pair of gate oxides using jet vapor deposition (JVD); and

forming the other of the pair of gate oxides to a second thickness; and

;

wiring the logic device to the memory device using a metallization process to implement a specific circuit function.

16. A method for fabricating a circuit having logic and memory devices on a single substrate, comprising:

forming a number of transistors on the substrate, wherein forming the number of transistors includes forming at least one transistor for use in a logic device and forming at least one transistor for use in a memory device on the substrate, and wherein forming the first transistor and the second transistor includes;

forming a pair of gate oxides to a first thickness on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers (nm) by atomic oxygen generated in high-density krypton plasma at approximately 400 degrees Celsius;

forming a thin layer of silicon nitride (Si₃N₄) on one of the pair of gate oxides using jet vapor deposition (JVD) such that a combined thickness for the thin layer of silicon nitride and gate oxide is less than 7 nanometers; and

forming the other of the pair of gate oxides to a second thickness; and

;

wiring the logic device to the memory device using a metallization process to implement a specific circuit function.

17. A method for fabricating a circuit having logic and memory devices on a single substrate, comprising:

forming a number of transistors on the substrate, wherein forming the number of transistors includes forming at least one transistor for use in a logic device and forming at least one transistor for use in a memory device on the substrate, and wherein forming the first transistor and the second transistor includes;

forming a pair of gate oxides to a first thickness on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers (nm) by atomic oxygen generated in high-density krypton plasma at approximately 400 degrees Celsius;

forming a thin layer of silicon nitride (Si₃N₄) on one of the pair of gate oxides using jet vapor deposition (JVD) such that a combined thickness for the thin layer of silicon nitride and gate oxide is less than 7 nanometers; and

forming the other of the pair of gate oxides to a second thickness such that the second thickness is less than 12 nanometers; and

wiring the logic device to the memory device using a metallization process to implement a specific circuit function.

18. A method for fabricating a circuit having logic and memory devices on a single substrate, comprising:

forming a number of transistors on the substrate, wherein forming the number of transistors includes forming at least one transistor for use in a logic device and forming at least one transistor for use in a memory device on the substrate, and wherein forming the first transistor and the second transistor includes;

forming a pair of gate oxides to a first thickness on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers (nm) by atomic oxygen generated in high-density krypton plasma at approximately 400 degrees Celsius;

forming a thin layer of silicon nitride (Si₃N₄) on one of the pair of gate oxides using jet vapor deposition (JVD) such that a combined thickness for the thin layer of silicon nitride and gate oxide is less than 7 nanometers for use in the logic device;

forming the other of the pair of gate oxides to a second thickness of less than 10 nanometers including the first thickness, which has not been etched, by a process using atomic oxygen generated in high-density krypton plasma at approximately 400 degrees Celsius for use in the memory device; and

forming a boron doped polysilicon gate on the thin dielectric layer as part of the logic device and on the other of the pair of gate oxides as part of the memory device; and

wiring the logic device to the memory device using a metallization process to implement a specific circuit function.

19. The method of claim 18, wherein forming a thin dielectric layer on one of the pair of gate oxides for use in the logic device is performed before forming the other of the pair of gate oxides to a second thickness.

20. The method of claim 18, wherein forming a thin dielectric layer on one of the pair of gate oxides includes forming a thin dielectric layer which exhibits a strong resistance to the formation of an interfacial oxide layer when forming the other of the pair of gate oxides to a second thickness.

21. A method for fabricating a circuit having logic and memory devices on a single substrate, comprising:

forming a number of transistors on the substrate, wherein forming the number of transistors includes forming at least one transistor for use in a logic device and forming at least one transistor for use in a memory device on the substrate, and wherein forming the first transistor and the second transistor includes;

forming a pair of gate oxides to a first thickness on the substrate, wherein forming the pair of gate oxides to a first thickness includes forming the pair of gate oxides to a thickness of less than 5 nanometers (nm) by atomic oxygen generated in high-density krypton plasma at approximately 400 degrees Celsius;

forming a thin layer of silicon nitride (Si₃N₄) on one of the pair of gate oxides using jet vapor deposition (JVD) wherein the silicon nitride layer has a thickness which is approximately a third of the first thickness of the gate oxide;

forming the other of the pair of gate oxides to a second thickness of less than 10 nanometers including the first thickness, which has not been etched, by a process using atomic oxygen generated in high-density krypton plasma at approximately 400 degrees Celsius for use in the memory device; and

forming a boron doped polysilicon gate on the thin dielectric layer as part of the logic device and on the other of the pair of gate oxides as part of the memory device; and

wiring the logic device to the memory device using a metallization process to implement a specific circuit function.