Multilayer capacitor structure having an array of concentric ring-shaped plates for deep sub-micron CMOS

• US 6,297,524 B1
• Filed: 04/04/2000
• Issued: 10/02/2001
• Est. Priority Date: 04/04/2000
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Sowlati, Tirdad, Vathulya, Vickram
• Primary Examiner(s): Flynn, Nathan
• Assistant Examiner(s): QUINTO, KEVIN V
• Application Number:
  US09/542,712
• Time in Patent Office: 546 Days
• Field of Search: 257/296, 257/298, 257/300, 257/301, 257/303, 257/308, 438/238, 438/239, 438/386, 438/242, 438/399
• US Class Current: 257/303
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 28/82 with an enlarged surface, e.g. formed by texturisation
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A capacitor structure having a first and at least a second conductor level of electrically conductive concentric ring-shaped lines. The conductive lines of the first and at least second levels are arranged in concentric ring-shaped stacks. A dielectric material is disposed between the first and second conductor levels and between the concentric conductive lines in each of the levels. At least one electrically conductive via electrically connects the conductive lines in each stack, thereby forming a concentric array of ring-shaped capacitor plates. The concentric array of capacitor plates are electrically connected in an alternating manner to first and second terminals of opposite polarity so that capacitance is generated between adjacent plates of the array. The capacitor structure is especially useful in deep sub-micron CMOS.

Claims

1. A capacitor comprising:

a first conductor level of electrically conductive concentric lines;

at least a second conductor level of electrically conductive concentric lines, the conductive lines of the first and at least second levels arranged in concentric stacks;

a dielectric material disposed between the first and second conductor levels and between the concentric conductive lines in each of the levels;

at least one electrically conductive via electrically connecting the conductive lines in each stack, thereby forming an array of concentric capacitor plates, each conductive via extending through the dielectric material between the first and second conductor levels; and

first and second terminals having opposite electrical polarities;

wherein the array of concentric capacitor plates are electrically connected in an alternating manner to the terminals of opposite polarity so that capacitance is generated between adjacent plates of the array.

2. The capacitor according to claim 1, wherein the conductive lines and the plates formed thereby have a ring-shaped structure.

3. The capacitor according to claim 1, wherein the conductive lines and the plates formed thereby have a square ring-shaped structure.

4. The capacitor according to claim 1, wherein the capacitor is constructed over a substrate.

5. The capacitor according to claim 4, wherein the substrate is made from a semiconductor material.

6. The capacitor according to claim 1, wherein the capacitor comprises a sub-micron MOS structure.

7. The capacitor according to claim 1, wherein the capacitor comprises a sub-micron CMOS structure.

8. The capacitor of claim 1, wherein the capacitor comprises a sub-micron structure.

9. The capacitor according to claim 1, wherein the conductive lines are made from one of a metal material and a conductive semiconductor material.

10. The capacitor according to claim 1, wherein the at least second conductor level of electrically conductive concentric lines is a plurality of conductor levels of electrically conductive concentric lines, the conductive lines of all the levels arranged in concentric stacks.

11. The capacitor according to claim 1, wherein the at least one electrically conductive via is a plurality of electrically conductive vias.