High performance, low power vertical integrated CMOS devices

• US 6,297,531 B2
• Filed: 01/05/1998
• Issued: 10/02/2001
• Est. Priority Date: 01/05/1998
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bertin, Claude L., Mandelman, Jack A., Armacost, Michael D., Hedberg, Erik L.
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US09/002,399
• Publication Number:
  US 20010002715A1
• Time in Patent Office: 1,366 Days
• Field of Search: 257/329, 257/330, 257/331, 257/334, 257/401, 257/369, 257/903
• US Class Current: 257/329
• CPC Class Codes: H01L 21/823885 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823821
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A vertical Field Effect Transistor (FET) that may be an N-type FET (NFET) or a P-type FET (PFET); a multi-device vertical structure that may be two or more NFETs or two or more PFETS; logic gates including at least one vertical FET or at least one multi-device vertical; a Static Random Access Memory (SRAM) cell and array including at least one vertical FET; a memory array including at least one such SRAM cell; and the process of forming the vertical FET structure, the vertical multi-device (multi-FET) structure, the logic gates and the SRAM cell. The vertical FETs are epitaxially grown layered stacks of NPN or PNP with the side of a polysilicon gate layer adjacent the device'"'"'s channel layer. The multi-FET structure may be formed by forming sides of two or more gates adjacent to the same channel layer or, by forming multiple channel layers in the same stack, e.g., PNPNP or NPNPN, each with its own gate, i.e., the side of a polysilicon gate layer. The SRAM cell may be radiation hardened by selectively thickening gate layers to increase storage node capacitance, providing high resistance cell wiring or by including a multi-layered gate oxide layer of NO or ONO, or by any combination thereof.

Claims

1. A Field Effect Transistor (FET) comprising:

a substrate;

a layered semiconductor stack having a channel layer of a first conduction type between a pair of layers of a second conduction type, wherein each of the layers in said semiconductor stack have the same width dimension;

a metallic wiring layer attached to said stack adjacent one of said pair of layers, said metallic wiring layer residing between said substrate and said one of said pair of layers;

a gate insulator layer on a sidewall of said semiconductor stack; and

a gate layer, only a first side of said gate layer adjacent said gate insulator layer extending substantially along said channel layer, said side forming a gate of the FET, and wherein said gate layer has the same thickness as and is in alignment with said channel layer.

2. The FET of claim 1 wherein semiconductor stack is a silicon stack.

3. The FET of claim 2 wherein the silicon stack is an epitaxially grown silicon stack.

4. The FET of claim 3 wherein the first conduction type is P-type and the second conduction type is N-type.

5. The FET of claim 3 wherein the first conduction type is N-type and the second conduction type is P-type.

6. The FET of claim 3 wherein the gate insulator layer comprises a layer of SiO₂.

7. The FET of claim 6 wherein the gate insulator layer further comprises a nitride layer.

8. The FET of claim 7 wherein the gate insulator layer comprises a layer of ONO.

9. The FET of claim 3 wherein the gate layer is a layer of polysilicon.

21. The FET of claim 1, wherein said pair of layers each have a thickness greater than a thickness of said channel layer.

22. The FET of claim 1, wherein a device channel length of said FET depends upon the thickness of said channel layer.

23. The FET of claim 1, wherein said pair of layers each have a same width.

24. The FET of claim 1, further comprising:

a plug layer adjacent one of an upper side and lower side of said gate layer;

an oxide spacer layer along the other of said upper side and lower side of said gate layer, said oxide spacer layer directly contacting one of said pair of layers and said plug layer being coplanar with the other of said pair of layers.

25. The FET of claim 24, wherein said plug layer and said one of an upper side and lower side of said gate layer having substantially the same width.

26. The FET of claim 24, wherein said oxide spacer layer and the other of said upper side and lower side of said gate layer having substantially the same width.

27. The FET of claim 24, further comprising:

a spacer adjacent a second side of said gate layer, said spacer separating the second side of said gate layer from an oxide layer.

10. An integrated circuit (IC) including a plurality of Field Effect Transistors (FETs), comprising:

a first layered epitaxial semiconductor stack having a first channel layer of a first conduction type between first and second layers of a second conduction type, wherein each of the layers in said first layered epitaxial semiconductor stack have a same width dimension;

a second layered epitaxial semiconductor stack having a second channel layer of said second conduction type between third and fourth layers of said first conduction type, wherein each of the layers in said second layered epitaxial semiconductor stack have a same width dimension;

gate insulator layers on sidewalls of said epitaxial semiconductor stacks; and

gate layers, only one side of each of said gate layers adjacent said gate insulator layers, said sides each forming a gate of first and second FETs, respectively,

wherein said gate layers are in alignment with said first and second channel layers, and wherein the first FET in the first layered epitaxial stack and the second FET in the second layered epitaxial stack form one inverter of a cross coupled pair of inverters in an SRAM cell.

11. The IC of claim 10 wherein each of the epitaxial semiconductor stacks are an epitaxially grown silicon stack.

12. The IC of claim 10, wherein the first conduction type is P-type and the second conduction type is N-type.

13. The IC of claim 10, wherein the first conduction type is N-type and the second conduction type is P-type.

14. A logic gate including at least one pair of Field Effect Transistors (FETs), said at least one pair of FETs comprising:

a layered epitaxial semiconductor stack having a first channel and a second channel of a first conduction type, said first channel being between first and second layers of a second conduction type and said second channel being between said second layer and a third layer of said second conduction type;

a first gate insulator layer on a first sidewall of said layered epitaxial semiconductor stack;

a second gate insulator layer on a second sidewall of said epitaxial semiconductor stack;

a first gate layer, only one side of said first gate layer adjacent said first gate insulator layer extending substantially along said first channel, said side of said first gate layer forming a first FET'"'"'s gate; and

a second gate layer, only one side of said second gate layer adjacent said second gate insulator layer extending substantially along said second channel, said side of said second gate layer forming a second FET'"'"'s gate.

15. The logic gate of claim 14 further comprising:

a second layered epitaxial semiconductor stack having a third channel of said second conduction type, said third channel being between fourth and fifth layers of said first conduction type;

third and fourth gate insulator layers on different sidewalls of said second layered epitaxial semiconductor stack;

a third gate layer, a side of said third gate layer adjacent said third gate insulator layer extending along said third channel, said side of said third gate layer forming a third FET'"'"'s gate;

a fourth gate layer, a side of said fourth gate layer adjacent said fourth gate insulator layer extending along said third channel, said side of said fourth gate layer forming a fourth FET'"'"'s gate; and

a strap, said fourth layer being connected by said strap to said third layer.

16. A logic gate including at least two pair of Field Effect Transistors (FETs), comprising:

a first layered epitaxial semiconductor stack having a first channel and a second channel of P-type, said first channel being between first and second layers of N-type and said second channel being between said second layer and a third layer of N-type;

a first sate insulator layer on a first sidewall of said first layered epitaxial semiconductor stack;

a second gate insulator layer on a second sidewall of said first layered epitaxial semiconductor stack;

a first gate layer, a side of said first gate layer adjacent said first gate insulator layer extending along said first channel, the side of said first gate layer forming a first FET'"'"'s gate;

a second gate layer, a side of said second gate layer adjacent said second gate insulator layer extending along said second channel, the side of said second gate layer forming a second FET'"'"'s gate;

a second layered epitaxial semiconductor stack having a third channel of N-type, said third channel being between fourth and fifth layers of P-type;

third and fourth gate insulator layers on different sidewalls of said second layered epitaxial semiconductor stack;

a third gate layer, a side of said third gate layer adjacent said third gate insulator layer extending along said third channel, the side of said third gate layer forming a third FET'"'"'s gate;

a fourth gate layer, a side of said fourth gate layer adjacent said fourth gate insulator layer extending along said third channel, the side of said fourth gate layer forming a fourth FET'"'"'s gate; and

a strap, said fourth layer being connected by said strap to said third layer,

wherein said logic gate is a NAND gate, a first input being connected to said first FET'"'"'s gate and said third FET'"'"'s gate, a second input being connected to said second FET'"'"'s gate and said fourth FET'"'"'s gate, and said strap being an output of said logic gate.

17. A logic gate including at least two pair of Field Effect Transistors (FETs), comprising:

a first Iavered epitaxial semiconductor stack having a first channel and a second channel of N-type, said first channel being between first and second layers of P-type and said second channel being between said second layer and a third layer of P-type;

a first gate insulator layer on a first sidewall of said first layered epitaxial semiconductor stack;

a second gate insulator layer on a second sidewall of said first layered epitaxial semiconductor stack;

a first gate layer, a side of said first gate layer adjacent said first gate insulator layer extending along said first channel, the side of said first gate layer forming a first FET'"'"'s gate;

a second gate layer, a side of said second gate layer adjacent said second gate insulator layer extending along said second channel, the side of said second gate layer forming a second FET'"'"'s gate;

a second layered epitaxial semiconductor stack having a third channel of P-type, said third channel being between fourth and fifth layers of N-type;

third and fourth gate insulator layers on different sidewalls of said second layered epitaxial semiconductor stack;

a third gate layer, a side of said third gate layer adjacent said third gate insulator layer extending along said third channel, the side of said third gate layer forming a third FET'"'"'s gate;

a fourth gate layer, a side of said fourth gate layer adjacent said fourth gate insulator layer extending along said third channel, the side of said fourth gate layer forming a fourth FET'"'"'s gate; and

a strap, said fourth layer being connected by said strap to said third layer,

wherein said logic gate is a NOR gate, a first input being connected to said first FET'"'"'s gate and said third FET'"'"'s gate, a second input being connected to said second FET'"'"'s gate and said fourth FET'"'"'s gate, and said strap being an output of said logic gate.

18. An array of SRAM cells, each of said SRAM cells comprising:

a pair of cross coupled inventors, each said inverters including a pair of vertical FETs, each of said vertical FETs comprising;

a layered epitaxial silicon stack, said layered epitaxial silicon stack comprising a source layer, a channel layer on said source layer and a drain layer on said channel layer,

a gate insulator layer at a sidewall of said channel layer, and

a polysilicon gate layer, a side of said gate extending substantially along said channel layer forming said FET'"'"'s gate; and

a pair of pass gates, each said pass gate being an individual said vertical FET and coupled to one side of said cross coupled inverters,

wherein the pair FETs in the cross coupled inverters are a PFET and a NFET, the pass gates are NFETs, and the polysilicon gate layer of the PFET is substantially thicker than the channel layer.

19. An array of SRAM cells, each of said SRAM cells comprising:

a pair of cross coupled inventors, each said inverters including a pair of vertical FETs, each of said vertical FETs comprising;

a layered epitaxial silicon stack, said layered epitaxial silicon stack comprising a source layer, a channel layer on said source layer and a drain layer on said channel layer,

a gate insulator layer at a sidewall of said channel layer, and

a polysilicon gate layer, a side of said gate extending substantially along said channel layer forming said FET'"'"'s gate;

a pair of pass gates, each said pass gate being an individual said vertical FET and coupled to one side of said cross coupled inverters; and

at least one resistive strap connecting the output of one of said inverters to the other inverter'"'"'s input, whereby a level change at said output is delayed from reaching said input,

wherein the pair FETs in the cross coupled inverters are a PFET and a NFET and the pass gates are NFETs.

20. The array of claim 19 wherein at least one resistive strap is two resistive straps, each of said resistive straps connecting the output of one of said inverters to the other inverter'"'"'s input, whereby a level change at one said output is delayed from reaching the other said input.

28. An integrated circuit, comprising:

a first layered epitaxial semiconductor stack having a first channel layer of a first conduction type between first and second layers of a second conduction type, and a second channel layer of said first conduction type between one of said first and second layers and a third layer of said second conduction type

a second layered epitaxial semiconductor stack having a third channel layer of said second conduction type between fourth and fifth layers of said first conduction type;

gate insulator layers on sidewalls of said epitaxial semiconductor stacks;

a first gate layer aligned with the first channel layer;

a second gate layer aligned with the second channel layer;

a third gate layer aligned with and adjacent one side of the third channel layer; and

a fourth gate layer aligned with and adjacent another side of the third channel layer,

wherein said first and second layers, said first channel layer, and the first gate layer form a first FET, and said one of said first and second layers, said third layer, said second channel layer, and the second gate layer form a second FET, and

wherein said fourth and fifth layers, third channel layer, and the third gate layer form a third FET, and said fourth and fifth layers and the fourth gate layer form a fourth FET.

29. The integrated circuit of claim 28, wherein the first, second, and third layers and the first and second channel layers in said first stack have a same width dimension, and wherein the fourth and fifth layers and the third channel layer in said second stack have a same width dimension.

30. The integrated circuit of claim 28, further comprising:

a metal layer contacting one of said fourth layer and said fifth layer;

a dielectric material formed on the metal layer;

a ground layer formed on the dielectric layer; and

an insulating layer formed on the ground layer.

31. The integrated circuit of claim 30, further comprising:

a semiconductor substrate attached to said insulating layer,

wherein none of said first gate layer, said second gate layer, said third gate layer, and said fourth gate layer are electrically linked.

32. The integrated circuit of claim 28, further comprising:

a wiring layer connected to at least one of the third gate layer and the fourth gate layer; and

an interconnect layer connected to said wiring layer.

33. The integrated circuit of claim 28, further comprising:

a wiring layer connected to at least one of the first gate layer and the second gate layer; and

an interconnect layer connected to said wiring layer.