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High performance, low power vertical integrated CMOS devices

  • US 6,297,531 B2
  • Filed: 01/05/1998
  • Issued: 10/02/2001
  • Est. Priority Date: 01/05/1998
  • Status: Expired due to Fees
First Claim
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1. A Field Effect Transistor (FET) comprising:

  • a substrate;

    a layered semiconductor stack having a channel layer of a first conduction type between a pair of layers of a second conduction type, wherein each of the layers in said semiconductor stack have the same width dimension;

    a metallic wiring layer attached to said stack adjacent one of said pair of layers, said metallic wiring layer residing between said substrate and said one of said pair of layers;

    a gate insulator layer on a sidewall of said semiconductor stack; and

    a gate layer, only a first side of said gate layer adjacent said gate insulator layer extending substantially along said channel layer, said side forming a gate of the FET, and wherein said gate layer has the same thickness as and is in alignment with said channel layer.

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