Power semiconductor device

• US 6,297,534 B1
• Filed: 10/07/1999
• Issued: 10/02/2001
• Est. Priority Date: 10/07/1998
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Nakamura, Kazutoshi, Kawaguchi, Yusuke, Nakagawa, Akio
• Primary Examiner(s): Flynn, Nathan
• Assistant Examiner(s): FORDE, REMMON R
• Application Number:
  US09/413,811
• Time in Patent Office: 726 Days
• Field of Search: 257/341, 257/342, 257/343, 257/401, 257/492, 257/493, 438/156, 438/268
• US Class Current: 257/341
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7824 with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors

Abstract

A first conductivity type active layer having high resistance is provided on an insulation region. A second conductivity type base layer is selectively formed on a surface of the first conductivity type active layer. A first conductivity type source layer is selectively formed on a surface of the second conductivity type base layer. A first conductivity type drain layer is selectively formed on a surface of the first conductivity type active layer. A gate electrode is formed facing, through a gate insulating film, a surface region of the second conductivity type base layer between the first conductivity type source layer and the first conductivity type active layer. A plurality of first and second conductivity type semiconductor regions are formed between the second conductivity type base layer and the first conductivity type drain layer. Each of the second conductivity type semiconductor regions is arranged alternately with each of the first conductivity type semiconductor regions. A drain current flows from the first conductivity type source layer to the first conductivity type drain layer through the first conductivity type semiconductor regions. Bottom portions of the second conductivity type semiconductor regions are shallower than the interface between the first conductivity type active layer and the insulation region. According to the present invention, low ON resistance and high withstand voltage are realized at the same time.

Claims

1. A power semiconductor device comprising:

a first conductivity type active layer provided on an insulation region;

a second conductivity type base layer selectively formed on a surface of said first conductivity type active layer;

a first conductivity type source layer selectively formed on a surface of said second conductivity type base layer;

a first conductivity type drain layer selectively formed on a surface of said first conductivity type active layer;

a gate electrode facing, through a gate insulating film, a surface region of said second conductivity type base layer between said first conductivity type source layer and said first conductivity type active layer;

a plurality of first and second conductivity type semiconductor regions formed between said second conductivity type base layer and said first conductivity type drain layer, each of said second conductivity type semiconductor regions arranged alternately with each of said first conductivity type semiconductor regions, a drain current flowing from said first conductivity type source layer to said first conductivity type drain layer through said first conductivity type semiconductor regions,

wherein said plurality of first and second conductivity type semiconductor regions are formed above said insulation region with said first conductivity type active layer interposed therebetween.

2. A power semiconductor device according to claim 1, wherein a dosage of a first conductivity type impurity in said first conductivity type active layer is in a range from 1.0×

10¹² cm<sup>−

2</sup> to 2.5×

10¹² cm<sup>−

2</sup>.

3. A power semiconductor device according to claim 1, wherein said plurality of first and second conductivity type semiconductor regions are arranged at a pitch of repetition of 0.1 μ

m to 5 μ

m.

4. A power semiconductor device according to claim 1, wherein an impurity dosage in said first conductivity type semiconductor regions and an impurity dosage in said second conductivity type semiconductor regions are in a range from 1.0×

10¹² cm<sup>−

2</sup> to 5.0×

10¹² cm<sup>−

2</sup> in a direction of arrangement thereof.

5. A power semiconductor device according to claim 1, wherein each of said plurality of first and second conductivity type semiconductor regions is formed in a striped pattern.

6. A power semiconductor device according to claim 1, wherein the insulation region is formed on a semiconductor substrate.

27. A power semiconductor device according to claim 1, wherein a dosage of a first conductivity type impurity to said first conductivity type active layer ranges from 1.0×

10¹² cm<sup>−

2</sup> to 2.5×

10¹² cm<sup>−

2</sup>,

a dosage to said first conductivity type semiconductor regions and a dosage to said second conductivity type semiconductor regions range from 1.0×

10¹² cm<sup>−

2</sup> to 5.0×

10¹² cm<sup>−

2</sup> in a direction of arrangement thereof, and

wherein said plurality of first and second conductivity type semiconductor regions are arranged at the pitch of repetition of 0.1 μ

m to 5 μ

m.

7. A power semiconductor device comprising:

a first conductivity type active layer provided on an insulation region;

a second conductivity type base layer selectively formed on a surface of said first conductivity type active layer;

a first conductivity type source layer selectively formed on a surface of said second conductivity type base layer;

a first conductivity type drain layer selectively formed on a surface of said first conductivity type active layer;

a gate electrode facing, through a gate insulating film, a surface region of said second conductivity type base layer between said first conductivity type source layer and said first conductivity type active layer;

a plurality of first and second conductivity type semiconductor regions formed between said second conductivity type base layer and said first conductivity type drain layer and formed above said insulation region with said first conductivity type active layer interposed therebetween, each of said second conductivity type semiconductor regions arranged alternately with each of said first conductivity type semiconductor regions and arranged in a direction crossing a direction from said first conductivity type source layer to said first conductivity type drain layer.

8. A power semiconductor device according to claim 7, wherein a dosage of a first conductivity type impurity in said first conductivity type active layer is in a range from 1.0×

10<sup>−

12</sup> cm<sup>−

2</sup> to 2.5×

1.0¹² cm<sup>−

2</sup>.

9. A power semiconductor device according to claim 7, wherein said plurality of first and second conductivity type semiconductor regions are arranged at a pitch of repetition of 0.1 μ

m to 5 μ

m.

10. A power semiconductor device according to claim 7, wherein an impurity dosage in said first conductivity type semiconductor regions and an impurity dosage in said second conductivity type semiconductor regions are in a range from 1.0×

10¹² cm<sup>−

2</sup> to 5.0×

10¹² cm<sup>−

2</sup> in a direction of arrangement thereof.

11. A power semiconductor device according to claim 7, wherein each of said plurality of first and second conductivity type semiconductor regions is formed in a striped pattern.

12. A power semiconductor device according to claim 7, wherein said first and second conductivity type semiconductor regions are arranged substantially perpendicularly to a direction from said first conductivity type source layer to said first conductivity type drain layer.

13. A power semiconductor device according to claim 7, wherein the insulation region is formed on a semiconductor substrate.

28. A power semiconductor device according to claim 7, wherein a dosage of a first conductivity type impurity to said first conductivity type active layer ranges from 1.0×

10¹² cm<sup>−

2</sup> to 2.5×

10¹² cm<sup>−

2</sup>,

a dosage to said first conductivity type semiconductor regions and a dosage to said second conductivity type semiconductor regions range from 1.0×

10¹² cm<sup>−

2</sup> to 5.0×

10¹² cm<sup>−

2</sup> in a direction of arrangement thereof, and

wherein said plurality of first and second conductivity type semiconductor regions are arranged at the pitch of repetition of 0.1 μ

m to 5 μ

m.

14. A power semiconductor device comprising:

a first conductivity type active layer provided on an insulation region;

a second conductivity type base layer selectively formed on a surface of said first conductivity type active layer;

a first conductivity type source layer selectively formed on a surface of said second conductivity type base layer;

a first conductivity type drain layer selectively formed on a surface of said first conductivity type active layer;

a gate electrode facing, through a gate insulating film, a surface region of said second conductivity type base layer between said first conductivity type source layer and said first conductivity type active layer;

a plurality of first and second conductivity type semiconductor regions formed between said second conductivity type base layer and said first conductivity type drain layer and formed on a surface of said first conductivity type active layer, each of said second conductivity type semiconductor regions arranged alternately with each of said first conductivity type semiconductor regions, a drain current flowing from said first conductivity type source layer to said first conductivity type drain layer through said first conductivity type semiconductor regions,

wherein said plurality of fist and second conductivity type semiconductor regions are formed above said insulation region with said first conductivity type active layer interposed therebetween, and

wherein said plurality of first and second conductivity type semiconductor regions are depleted from junction interfaces thereof before a depletion layer extending from a surface of said insulation region reaches bottom portions of said second conductivity type semiconductor regions.

15. A power semiconductor device comprising:

a first conductivity type active layer formed on a second conductivity type semiconductor substrate;

a second conductivity type base layer selectively formed on a surface of said first conductivity type active layer;

a first conductivity type source layer selectively formed on a surface of said second conductivity type base layer;

a first conductivity type drain layer selectively formed on a surface of said first conductivity type active layer;

a gate electrode facing, through a gate insulating film, a surface region of said second conductivity type base layer between said first conductivity type source layer and said first conductivity type active layer;

a plurality of first and second conductivity type semiconductor regions formed between said second conductivity type base layer and said first conductivity type drain layer, each of said second conductivity type semiconductor regions arranged alternately with each of said first conductivity type semiconductor regions, a drain current flowing from said first conductivity type source layer to said first conductivity type drain layer through said first conductivity type semiconductor regions,

wherein said plurality of first and second conductivity type semiconductor regions are formed above said second conductivity type semiconductor substrate with said first conductivity type active layer interposed therebetween.

16. A power semiconductor device according to claim 15, wherein a dosage of a first conductivity type impurity in said first conductivity type active layer is in a range from 1.0×

10¹² cm<sup>−

2</sup> to 2.5×

10¹² cm<sup>−

2</sup>.

17. A power semiconductor device according to claim 15, wherein said plurality of first and second conductivity type semiconductor regions are arranged at a pitch of repetition of 0.1 μ

m to 5 μ

m.

18. A power semiconductor device according to claim 15, wherein an impurity dosage in said first conductivity type semiconductor regions and an impurity dosage in said second conductivity type semiconductor regions are in a range from 1.0×

10¹² cm<sup>−

2</sup> to 5.0×

10¹² cm<sup>−

2</sup> in a direction of arrangement thereof.

19. A power semiconductor device according to claim 15, wherein each of said plurality of first and second conductivity type semiconductor regions is formed in a striped pattern.

29. A power semiconductor device according to claim 15, wherein a dosage of a first conductivity type impurity to said first conductivity type active layer ranges from 1.0×

10¹² cm<sup>−

2</sup> to 2.5×

10¹² cm<sup>−

2</sup>,

a dosage to said first conductivity type semiconductor regions and a dosage to said second conductivity type semiconductor regions range from 1.0×

10¹² cm<sup>−

2</sup> to 5.0×

10¹² cm<sup>−

2</sup> in a direction of arrangement thereof, and

wherein said plurality of first and second conductivity type semiconductor regions are arranged at the pitch of repetition of 0.1 μ

m to 5 μ

m.

20. A power semiconductor device comprising:

a first conductivity type active layer formed on a second conductivity type semiconductor substrate;

second conductivity type base layer selectively formed on a surface of said first conductivity type active layer;

a first conductivity type source layer selectively formed on a surface of said second conductivity type base layer;

a first conductivity type drain layer selectively formed on a surface of said first conductivity type active layer;

a gate electrode facing, through a gate insulating film, a surface region of said second conductivity type base layer between said first conductivity type source layer and said first conductivity type active layer;

a plurality of first and second conductivity type semiconductor regions formed between said second conductivity type base layer and said first conductivity type drain layer and formed above said second conductivity type semiconductor substrate with said first conductivity type active layer interposed therebetween, each of said second conductivity type semiconductor regions arranged alternately with each of said first conductivity type semiconductor regions and arranged in a direction crossing a direction from said first conductivity type source layer to said first conductivity type drain layer.

21. A power semiconductor device according to claim 20, wherein a dosage of a first conductivity type impurity in said first conductivity type active layer is in a range from 1.0×

10¹² cm<sup>−

2</sup> to 2.5×

10¹² cm<sup>−

2</sup>.

22. A power semiconductor device according to claim 20, wherein said plurality of first and second conductivity type semiconductor regions are arranged at a pitch of repetition of 0.1 μ

m to 5 μ

m.

23. A power semiconductor device according to claim 20, wherein an impurity dosage in said first conductivity type semiconductor regions and an impurity dosage in said second conductivity type semiconductor regions are in a range from 1.0×

10¹² cm<sup>−

2</sup> to 5.0×

10¹² cm<sup>−

2</sup> in a direction of arrangement thereof.

24. A power semiconductor device according to claim 20, wherein each of said plurality of first and second conductivity type semiconductor regions is formed in a striped pattern.

25. A power semiconductor device according to claim 20, wherein said first and second conductivity type semiconductor regions are arranged substantially perpendicularly to a direction from said first conductivity type source layer to said first conductivity type drain layer.

30. A power semiconductor device according to claim 20, wherein a dosage of a first conductivity type impurity to said first conductivity type active layer ranges from 1.0×

10¹² cm<sup>−

2</sup> to 2.5×

10¹² cm<sup>−

2</sup>,

a dosage to said first conductivity type semiconductor regions and a dosage to said second conductivity type semiconductor regions range from 1.0×

10¹² cm<sup>−

2</sup> to 5.0×

10¹² cm<sup>−

2</sup> in a direction of arrangement thereof, and

wherein said plurality of first and second conductivity type semiconductor regions are arranged at the pitch of repetition of 0.1 μ

m to 5 μ

m.

26. A power semiconductor device comprising:

a first conductivity type active layer formed on a second conductivity type semiconductor substrate;

a second conductivity type base layer selectively formed on a surface of said first conductivity type active layer;

a first conductivity type source layer selectively formed on a surface of said second conductivity type base layer;

a first conductivity type drain layer selectively formed on a surface of said first conductivity type active layer;

a gate electrode facing, through a gate insulating film, a surface region of said second conductivity type base layer between said first conductivity type source layer and said first conductivity type active layer;

a plurality of first and second conductivity type semiconductor regions formed between said second conductivity type base layer and said first conductivity type drain layer and formed on a surface of said first conductivity type active layer, each of said second conductivity type semiconductor regions arranged alternately with each of said first conductivity type semiconductor regions, a drain current flowing from said first conductivity type source layer to said first conductivity type drain layer through said first conductivity type semiconductor regions,

wherein said plurality of first and second conductivity type semiconductor regions are formed above said second conductivity type semiconductor substrate with said first conductivity type active layer interposed therebetween, and

wherein said plurality of first and second conductivity type semiconductor regions are completely depleted from junction interfaces thereof before a depletion layer extending from a surface of said second conductivity type semiconductor substrate reaches bottom portions of said second conductivity type semiconductor regions.