Stackable ceramic FBGA for high thermal applications

• US 6,297,548 B1
• Filed: 06/30/1999
• Issued: 10/02/2001
• Est. Priority Date: 06/30/1998
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Corisis, David J., Kinsman, Larry D., Moden, Walter L., Mess, Leonard E.
• Primary Examiner(s): Graybill, David E.
• Application Number:
  US09/344,279
• Time in Patent Office: 825 Days
• Field of Search: 257/686, 257/687, 257/725, 257/730, 257/731, 257/732, 257/733, 257/777
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06572 Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 2225/06586 Housing with external bump or bump-like connectors
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15165 : Monolayer substrate
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1627 : stacked type assemblies, e.g. stacked multi-cavities
• CPC Class Codes: H01L 2924/3011 : Impedance

Abstract

An apparatus package for high temperature thermal applications for ball grid array semiconductor devices and a method of packaging ball grid array semiconductor devices.

Claims

1. An assembly comprising:

a first carrier having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, a first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the at least one second circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the first carrier.

2. The assembly of claim 1, further comprising:

a substrate having an upper surface, a lower surface, and at least one circuit on the upper surface thereof; and

at least one second connector connected to the at least one connection pad on the lower surface of the first carrier and the at least one circuit on the upper surface of the substrate.

3. The assembly of claim 1, wherein the first carrier includes at least one fin on a portion thereof.

4. The assembly of claim 1, further comprising:

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, at least one first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one second circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the first carrier.

5. The assembly of claim 1, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

6. An assembly comprising:

a first carrier having a cavity therein, an upper surface, a lower surface, at least one aperture extending therethrough, and at least one circuit located in a portion of the cavity extending to the at least one aperture;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the at least one circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier; and

connector material located in the at least one aperture in the first carrier.

7. The assembly of claim 6, further comprising:

a substrate having an upper surface, a lower surface, and at least one circuit on the upper surface thereof; and

at least one second connector connected to the connector material in the at least one aperture in the first carrier and the at least one circuit on the upper surface of the substrate.

8. The assembly of claim 6, wherein the first carrier includes at least one fin on a portion thereof.

9. The assembly of claim 6, further comprising:

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one aperture therethrough, and at least one circuit located in a portion of the cavity connected to the at least one aperture;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier; and

connector material located in a second aperture in the second carrier connected to the connector material in the at least one aperture in the first carrier.

10. The assembly of claim 6, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

11. A semiconductor device assembly comprising:

a first carrier having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, a first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the at least one second circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the first carrier.

12. The semiconductor device assembly of claim 11, further comprising:

a substrate having an upper surface, a lower surface, and the at least one second circuit on the upper surface thereof; and

at least one second connector connected to the at least one connection pad on the lower surface of the first carrier and the at least one second circuit on the upper surface of the substrate.

13. The semiconductor device assembly of claim 11, wherein the first carrier includes at least one fin on a portion thereof.

14. The semiconductor device assembly of claim 11, further comprising:

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, a first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one second circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the first carrier.

15. The semiconductor device assembly of claim 11, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

16. A semiconductor device assembly comprising:

a first carrier having a cavity therein, an upper surface, a lower surface, at least one aperture extending therethrough, and at least one circuit located in a portion of the cavity extending to the at least one aperture;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the at least one circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier; and

connector material located in the at least one aperture in the first carrier.

17. The semiconductor assembly of claim 16, further comprising:

a substrate having an upper surface, a lower surface, and at least one circuit on the upper surface thereof; and

at least one second connector connected to the connector material in the at least one aperture in the first carrier and the at least one circuit on the upper surface of the substrate.

18. The semiconductor device assembly of claim 16, wherein the first carrier includes at least one fin on a portion thereof.

19. The semiconductor device assembly of claim 16, further comprising:

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one aperture therethrough, and at least one circuit located in a portion of the cavity connected to the at least one aperture;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier; and

connector material located in a second aperture in the second carrier connected to the connector material in the at least one aperture in the first carrier.

20. The semiconductor device assembly of claim 16, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

21. An assembly comprising:

a substrate having an upper surface, a lower surface, and at least one circuit on the upper surface thereof,

a first carrier having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, at least one first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the at least one second circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier; and

at least one second connector connected to the at least one connection pad on the lower surface of the first carrier and the at least one first circuit on the upper surface of the substrate.

22. The assembly of claim 21, wherein the first carrier includes at least one fin on a portion thereof.

23. The assembly of claim 21, further comprising:

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, a first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one second circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the first carrier.

24. The assembly of claim 21, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

25. An assembly comprising:

a substrate having an upper surface, a lower surface, and at least one circuit on the upper surface thereof;

a first carrier having a cavity therein, an upper surface, a lower surface, at least one aperture extending therethrough, and at least one circuit located in a portion of the cavity extending to the at least one aperture;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the at least one circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier;

connector material located in the at least one aperture in the carrier; and

at least one second connector connected to the connector material in the at least one aperture in the first carrier and the at least one circuit on the upper surface of the substrate.

26. The assembly of claim 25, wherein the first carrier includes at least one fin on a portion thereof.

27. The assembly of claim 25, further comprising:

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one aperture therethrough, and at least one circuit located in a portion of the cavity connected to the at least one aperture;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier; and

connector material located in a second aperture in the second carrier connected to the connector material in the at least one aperture in the first carrier.

28. The assembly of claim 25, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of the bottom surface thereof.

29. A semiconductor device assembly comprising:

a substrate having an upper surface, a lower surface, and at least one circuit on the upper surface thereof;

a first carrier having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, at least one first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the at least one second circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier; and

at least one second connector connected to the at least one connection pad on the lower surface of the first carrier and the at least one first circuit on the upper surface of the substrate.

30. The semiconductor device assembly of claim 29, wherein the first carrier includes at least one fm on a portion thereof.

31. The semiconductor device assembly of claim 29, further comprising:

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, a first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one second circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the first carrier.

32. The semiconductor device assembly of claim 29, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

33. A semiconductor device assembly comprising:

a substrate having an upper surface, a lower surface, and at least one first circuit on the upper surface thereof;

a first carrier having a cavity therein, an upper surface, a lower surface, at least one aperture extending therethrough, and at least one second circuit located in a portion of the cavity extending to the at least one aperture;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the at least one second circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier;

connector material located in the at least one aperture in the carrier; and

at least one second connector connected to the connector material in the at least one aperture in the first carrier and the at least one first circuit on the upper surface of the substrate.

34. The semiconductor device assembly of claim 33, wherein the first carrier includes at least one fin on a portion thereof.

35. The semiconductor device assembly of claim 33, further comprising:

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one aperture therethrough, and at least one circuit located in a portion of the cavity connected to the at least one aperture;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the second carrier;

a first connector between the at least one circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier; and

connector material located in a second aperture in the second carrier connected to the connector material in the at least one aperture in the first carrier.

36. The semiconductor device assembly of claim 33, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

37. An assembly comprising:

a substrate having an upper surface, a lower surface, and at least one circuit on the upper surface thereof;

a first carrier having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, at least one first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to one of the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a first semiconductor device having an active surface having at least one bond pad thereon, the first semiconductor device located within the cavity of the first carrier;

a first connector between the at least one second circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the first semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier;

at least one second connector connected to the at least one connection pad on the lower surface of the first carrier and the at least one first circuit on the upper surface of the substrate;

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, at least one first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a second semiconductor device having an active surface having at least one bond pad thereon, the second semiconductor device located within the cavity of the second carrier;

a second connector between the at least one second circuit located in a portion of the cavity of the second carrier and the at least one bond pad on the active surface of the second semiconductor device;

encapsulant material filling a portion of the cavity in the second carrier;

at least one third connector connected to the at least one connection pad on the lower surface of the second carrier and the at least one first circuit on the lower surface of the substrate.

38. The assembly of claim 37, wherein the first carrier includes at least one fin on a portion thereof.

39. The assembly of claim 37, further comprising:

a third carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, a first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a third semiconductor device having an active surface having at least one bond pad thereon, the third semiconductor device located within the cavity of the third carrier;

a fourth connector between the at least one first circuit located in a portion of the cavity of the third carrier and the at least one bond pad on the active surface of the semiconductor device; and

encapsulant material filling a portion of the cavity in the third carrier.

40. The assembly of claim 37, wherein the first carrier includes a first frustoconical surface on a portion thereof, a second frustoconical surface on another portion thereof, and a lip on a portion of a bottom surface thereof.

41. An assembly comprising:

a substrate having an upper surface, a lower surface, and at least one circuit on the upper surface thereof;

a first carrier having a cavity therein, an upper surface, a lower surface, at least one aperture extending therethrough, and the at least one circuit located in a portion of the cavity extending to the at least one aperture;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the at least one circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier;

a first connector material located in the at least one aperture in the carrier;

at least one second connector connected to the first connector material in the at least one aperture in the first carrier and the at least one circuit on the upper surface of the substrate;

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, at least one first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a second semiconductor device having an active surface having at least one bond pad thereon, the second semiconductor device located within the cavity of the second carrier;

a second connector between the at least one second circuit located in a portion of the cavity of the second carrier and the at least one bond pad on the active surface of the second semiconductor device;

encapsulant material filling a portion of the cavity in the second carrier;

at least one third connector connected to the at least one connection pad on the lower surface of the second carrier and the at least one first circuit on the lower surface of the substrate.

42. The assembly of claim 41, wherein the first carrier includes at least one fin on a portion thereof.

43. The assembly of claim 41, further comprising:

a third carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, at least one first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a third semiconductor device having an active surface having at least one bond pad thereon, the third semiconductor device located within the cavity of the third carrier;

a fourth connector between the at least one second circuit located in a portion of the cavity of the third carrier and the at least one bond pad on the active surface of the third semiconductor device; and

encapsulant material filling a portion of the cavity in the third carrier.

44. An semiconductor device assembly comprising:

a substrate having an upper surface, a lower surface, and at least one circuit on the upper surface thereof;

a first carrier having a cavity therein, an upper surface, a lower surface, at least one aperture extending therethrough, and the at least one circuit located in a portion of the cavity extending to the at least one aperture;

a semiconductor device having an active surface having at least one bond pad thereon, the semiconductor device located within the cavity of the first carrier;

a first connector between the at least one circuit located in a portion of the cavity of the first carrier and the at least one bond pad on the active surface of the semiconductor device;

encapsulant material filling a portion of the cavity in the first carrier;

a first connector material located in the at least one aperture in the first carrier;

at least one second connector connected to the first connector material located in the at least one aperture in the first carrier and the at least one circuit on the upper surface of the substrate;

a second carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, at least one first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a second semiconductor device having an active surface having at least one bond pad thereon, the second semiconductor device located within the cavity of the second carrier;

a second connector between the at least one second circuit located in a portion of the cavity of the second carrier and the at least one bond pad on the active surface of the second semiconductor device;

encapsulant material filling a portion of the cavity in the second carrier;

at least one third connector connected to the at least one connection pad on the lower surface of the second carrier and the at least one first circuit on the lower surface of the substrate.

45. The assembly of claim 44, wherein the first carrier includes at least one fin on a portion thereof.

46. The assembly of claim 44, further comprising:

a third carrier oriented with respect to the first carrier and positioned the same direction as the first carrier further having a cavity therein, an upper surface, a lower surface, at least one connection pad on the upper surface, at least one connection pad on the lower surface, a first circuit connecting the at least one connection pad on the upper surface to the at least one connection pad on the lower surface, and at least one second circuit located in a portion of the cavity connected to the at least one connection pad on the upper surface and the at least one connection pad on the lower surface;

a third semiconductor device having an active surface having at least one bond pad thereon, the third semiconductor device located within the cavity of the third carrier;

a fourth connector between the at least one first circuit located in a portion of the cavity of the third carrier and the at least one bond pad on the active surface of the third semiconductor device; and

encapsulant material filling a portion of the cavity in the third carrier.