Semiconductor device having an internal voltage generating circuit

• US 6,297,624 B1
• Filed: 02/26/1999
• Issued: 10/02/2001
• Est. Priority Date: 06/26/1998
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Furutani, Kiyohiro, Kono, Takashi, Mitsui, Katsuyoshi
• Primary Examiner(s): HAN, YOUNGHUIE JESSICA
• Application Number:
  US09/258,159
• Time in Patent Office: 949 Days
• Field of Search: 323/312, 323/313, 323/314, 323/315, 323/316, 327/52, 327/53, 327/54, 365/226
• US Class Current: 323/316
• CPC Class Codes: G05F 1/465 Internal voltage generators for integrated circuits, e.g. step down generators

Abstract

An internal power supply circuit produces an internal power supply voltage from an external power supply voltage. A voltage level control circuit controls a voltage level and a temperature characteristic of the internal power supply voltage generated by the internal power supply circuit. The internal power supply circuit produces the internal power supply voltage having a negative or zero temperature characteristic in a low temperature region and a positive temperature characteristic in a high temperature region. The voltage level control circuit includes a structure optimizing a capacitance value of a sense power supply line stabilizing capacitance for driving a sense amplifier circuit, a level converting circuit determining the lowest operable region of the external power supply voltage of the internal power supply circuit, or a structure forcedly operating the internal voltage down converter upon power-on. The internal power supply voltage at a desired level is stably produced with a small occupied area and a low current consumption.

Claims

1. A semiconductor device comprising:

a current drive transistor coupled between an external power supply node receiving an externally supplied power supply voltage and an internal power supply line transmitting an internal power supply voltage;

a level converting circuit receiving a reference voltage and the internal power supply voltage on said internal power supply line, for level-converting said reference voltage and said internal power supply voltage for outputting; and

a comparing circuit for making a comparison between a level-converted reference voltage and a level-converted internal power supply voltage received from said level converting circuit, to adjust a conductance of said current drive transistor in accordance with a result of said comparison.

2. The semiconductor device according to claim 1, wherein said comparing circuit includes:

a current mirror stage coupled to said external power supply node for supplying a current; and

a pair of insulated gate field effect transistors connected between said current mirror stage and a ground node and receiving the level-converted internal power supply voltage and the level-converted reference voltage on their gates, respectively, wherein a first conduction node of each of said pair of insulated gate field effect transistors is coupled to receive the ground voltage.

3. The semiconductor device according to claim 1, wherein said level converting circuit includes:

a first insulated gate field effect transistor coupled between first and second nodes and receiving said internal power supply voltage on a gate thereof;

a second insulated gate field effect transistor coupled between the first node and a third node and receiving said reference voltage on a gate thereof;

a third insulated gate field effect transistor coupled between said second node and a ground node and having a gate coupled to said third node; and

a fourth insulated gate field effect transistor coupled between said third node and said ground node and having a gate coupled to said third node,

said level-converted reference voltage being generated from said third node, said level-converted internal power supply voltage being generated from said second node, and the first to fourth insulated gate field effect transistors being of a common conductivity type.

4. The semiconductor device according to claim 1, wherein said level converting circuit includes:

a first insulated gate field effect transistor coupled between a first node and a second node, and receiving said internal power supply voltage on a gate thereof;

a second insulated gate field effect transistor coupled between the first node and a third node, and receiving said reference voltage on a gate thereof;

a third insulated gate field effect transistor coupled between the second node and a ground node, and having a gate coupled to said second node; and

a fourth insulated gate field effect transistor coupled between said third node and the ground node, and having a gate coupled to said second node;

said level-converted internal power supply voltage being generated at said second node, and said level-converted reference voltage being generated at said third node, and

the first to fourth insulated gate field effect transistors being the same in conducting type.

5. A semiconductor device comprising:

a delay chain including a plurality of delay stages connected in series, receiving an operation mode instructing signal for delaying;

decode circuitry for decoding signals on a plurality of predetermined nodes of said delay chain to produce an activating signal;

a voltage down converter activated in response to activation of the activating signal from said decode circuitry, for adjusting a voltage level of an internal power supply voltage in accordance with a difference between said internal power supply voltage and a reference voltage, said voltage down converter including a first down-converter circuit for generating a first internal power supply voltage, and a second down-converter circuit for generating a second internal power supply voltage higher than said first internal power supply voltage;

a plurality of memory cells arranged in rows and columns;

sense amplifiers provided corresponding to the columns, receiving the internal power supply voltage from the voltage down converter for sensing and amplifying data on corresponding columns when activated in response to activation of said operation mode instructing signal; and

a selector coupled to said voltage down converter, for selecting the second internal power supply voltage for application to said sense amplifiers in response to deactivation of said operation mode instructing signal.

6. A semiconductor device comprising:

a delay chain including a plurality of delay stages connected in series, receiving an operation mode instructing signal for delaying;

decode circuitry for decoding signals on a plurality of predetermined nodes of said delay chain to produce an activating signal; and

a voltage down converter activated in response to activation of the activating signal from said decode circuitry, for adjusting a voltage level of an internal power supply voltage in accordance with a difference between said internal power supply voltage and a reference voltage, said voltage down converter including a comparison circuit for making a comparison between said internal power supply voltage and said reference voltage, and a current drive transistor for supplying a current from an external power supply node to an internal power supply line transmitting said internal power supply voltage in accordance with the output signal of the comparison circuit, wherein

said decode circuitry includes a circuit for producing a first activating signal activating said voltage down converter, and a second activating signal increasing an operation current of the comparison circuit of the voltage down converter for a predetermined period upon activation thereof.

7. The semiconductor device according to claim 6, wherein said circuit included in said decode circuitry activates said second activating signal in response to shifting to activation and deactivation of said operation mode instructing signal.

8. The semiconductor device according to claim 6, further comprising;

a plurality of memory cells arranged in rows and columns; and

sense amplifiers provided corresponding to the columns, receiving the internal power supply voltage from the voltage down converter for sensing and amplifying data on corresponding columns when activated in response to activation of said operation mode instructing signal.

9. A semiconductor device comprising:

a delay chain including a plurality of delay stages connected in series, receiving an operation mode instructing signal for delaying;

decode circuitry for decoding signals on a plurality of predetermined nodes of said delay chain to produce an activating signal; and

a voltage down converter activated in response to activation of the activating signal from said decode circuitry, for adiusting a voltage level of an internal power supply voltage in accordance with a difference between said internal power supply voltage and a reference voltage,

said decode circuitry including a circuit for producing a first activating signal activating said voltage down converter, and a second activating signal increasing an operation current of the comparison circuit of the voltage down converter for a predetermined period upon activation thereof, wherein

said voltage down converter includes first and second internal voltage down converters producing the internal power supply voltages at different voltage levels, respectively, and the first and second activating signals are applied to said first and second internal voltage converters, respectively.

10. A semiconductor device comprising:

a delay chain including a plurality of delay stages connected in series, receiving an operation mode instructing signal for delaying;

decode circuitry for decoding signals on a plurality of predetermined nodes of said delay chain to produce an activating signal, said decode circuitry including a circuit for producing a first activating signal activating said voltage down converter, and a second activating signal increasing an operation current of the comparison circuit of the voltage down converter for a predetermined period upon activation thereof; and

a voltage down converter activated in response to activation of the activating signal from said decode circuitry, for adjusting a voltage level of an internal power supply voltage in accordance with a difference between said internal power supply voltage and a reference voltage, said voltage down converter including first and second internal voltage down converters producing the internal power supply voltages at different voltage levels, respectively, and the first and second activating signals both being applied to said first internal voltage converter.

11. A semiconductor device comprising:

a current drive transistor coupled between an external power supply node receiving an external power supply voltage and an internal power supply line;

comparing circuitry for making a comparison between voltages corresponding to a reference voltage and an internal power supply voltage on said internal power supply line, respectively, to control a conductance of said current drive transistor in accordance with the result of said comparison when made active; and

activating circuitry for activating said comparing circuitry in accordance with a level of said internal power supply voltage.

12. The semiconductor device according to claim 11, wherein

said activating circuitry includes a circuit for activating said comparing circuitry in accordance with a difference between said internal power supply voltage and said reference voltage.

13. The semiconductor device according to claim 11, wherein

said activating circuitry includes a circuit for activating said comparing circuitry in accordance with a difference between a criterion voltage other than said reference voltage and said internal power supply voltage.

14. The semiconductor device according to claim 11, wherein

said activating circuitry includes a circuit for activating said comparing circuitry in accordance with a difference between said internal power supply voltage and said external power supply voltage.

15. The semiconductor device according to claim 11, wherein

said activating circuit includes a circuitry for activating said comparing circuitry when a difference between said internal and external power supply voltages becomes not higher than a predetermined value.