Test carrier with variable force applying mechanism for testing semiconductor components

• US 6,297,660 B2
• Filed: 12/12/2000
• Issued: 10/02/2001
• Est. Priority Date: 01/13/1999
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farnworth, Warren M., Wark, James M., Akram, Salman, Gochnour, Derek
• Primary Examiner(s): Karlsen, Ernest
• Assistant Examiner(s): TANG, MINH NHUT
• Application Number:
  US09/734,514
• Publication Number:
  US 20010000295A1
• Time in Patent Office: 294 Days
• Field of Search: 324/754, 324/755, 324/758, 324/757, 324/765, 324/762, 324/158.1
• US Class Current: 324/756.02
• CPC Class Codes: G01R 1/0466 concerning contact pieces or mechanical details, e.g. hinges or cams; Shielding

Abstract

A semiconductor carrier for testing semiconductor components, such as bare dice and chip scale packages, and a method for testing components using the carrier, are provided. The carrier includes a base, an interconnect for making temporary electrical connections with the component, and a force applying mechanism for biasing the component against the interconnect. The force applying mechanism includes an elastomeric biasing member adapted to apply a relatively large biasing force during assembly of the carrier and a smaller biasing force in the assembled carrier. The force applying mechanism also includes a pressure plate which can include a cushioning layer with a non-stick surface for contacting the component. In addition, the cushioning layer, and elastomeric biasing member can be made of conductive elastomers to provide an electrical path from a backside of the component.

Claims

1. A method for testing a semiconductor component comprising:

providing a test carrier comprising a base configured to retain the component, an interconnect configured to make electrical connections with the component, and an elastomeric biasing member configured to bias the component and the interconnect together, the biasing member comprising a tubular element having a width, an opening and segments on either side of the opening;

assembling the carrier to provide an assembled carrier containing the component on the interconnect;

flattening the biasing member during the assembly step to close the opening and exert a first biasing force across the width to make the electrical connections;

compressing the biasing member in the assembled carrier to exert a second biasing force across the segments to maintain the electrical connections; and

transmitting test signals through the electrical connections to the component.

2. The method of claim 1 wherein the biasing member comprises a material selected from the group consisting of silicone, fluorsilicone, butyl rubber, polyimide and conductive polymer.

3. The method of claim 1 wherein the biasing member comprises a metal or polymer outer layer configured to prevent adhesion to the component.

4. The method of claim 1 wherein the flattening step is performed by overdriving the biasing member in a z-direction.

5. The method of claim 1 wherein the compressing step is performed by selection of a geometry of the carrier and the biasing member.

6. A method for testing a semiconductor component comprising:

providing a test carrier comprising a base configured to retain the component, an interconnect configured to make electrical connections with the component, and an elastomeric biasing member with an accordion shape configured to bias the component and the interconnect together;

assembling the carrier to provide an assembled carrier containing the component on the interconnect;

flattening the biasing member during the assembly step to exert a first biasing force to make the electrical connections;

compressing the biasing member in the assembled carrier into the accordion shape to exert a second biasing force to maintain the electrical connections; and

transmitting test signals through the electrical connections to the component.

7. The method of claim 6 wherein the flattening step is performed by overdriving the biasing member in a z-direction.

8. The method of claim 6 wherein the compressing step is performed by selection of a geometry of the carrier and the biasing member.

9. A method for testing a semiconductor component comprising:

providing a carrier configured to hold the component;

providing an interconnect on the carrier configured to make temporary electrical connections with the component;

providing an elastomeric biasing member on the carrier with a wave shape configured to bias the component and the interconnect together;

assembling the carrier to provide an assembled carrier containing the component on the interconnect;

flattening the biasing member during the assembly step to exert a first biasing force to make the electrical connections;

compressing the biasing member in the assembled carrier into the wave shape to exert a second biasing force to maintain the electrical connections; and

transmitting test signals through the electrical connections to the component.

10. The method of claim 9 wherein the flattening step is performed by overdriving the biasing member in a z-direction.

11. The method of claim 9 wherein the compressing step is performed by selection of a geometry of the carrier and the biasing member.

12. A method for testing a semiconductor component comprising:

providing a test carrier comprising a base configured to retain the component, an interconnect configured to make electrical connections with the component, and an elastomeric biasing member configured to bias the component and the interconnect together, the biasing member having a geometry selected to provide a first biasing force for making the electrical connections and a second biasing force for maintaining the electrical connections;

assembling the carrier to provide an assembled carrier containing the component on the interconnect;

overdriving the biasing member in a z-direction during the assembly step to flatten the biasing member and exert the first biasing force;

compressing the biasing member in the assembled carrier to exert the second biasing force; and

transmitting test signals through the electrical connections to the component.

13. The method of claim 12 wherein the geometry of the biasing member and a configuration of the carrier are selected to perform the compressing step.

14. The method of claim 12 wherein the biasing member comprises a tubular element having an opening and segments on either side of the opening configured to exert the second biasing force.

15. The method of claim 12 wherein the biasing member comprise a wave shaped element.

16. The method of claim 12 wherein the biasing member comprise an accordion shaped element.

17. The method of claim 12 wherein the first biasing force is from two to ten times the second biasing force.

18. The method of claim 12 wherein the biasing member comprises a material selected from the group consisting of silicone, fluorsilicone, butyl rubber, polyimide and conductive polymer.