Serial device compaction for improving integrated circuit layouts

• US 6,297,668 B1
• Filed: 11/23/1999
• Issued: 10/02/2001
• Est. Priority Date: 11/25/1998
• Status: Expired due to Fees

• Current Assignee: Innurvation IP LLC
• Original Assignee: Manopower Technologies Incorporated
• Inventors: Schober, Robert C.
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Tran, Anh Q.
• Application Number:
  US09/448,623
• Time in Patent Office: 679 Days
• Field of Search: 326/101, 326/102, 326/103, 326/112, 326/119, 326/121, 257/206, 257/204
• US Class Current: 326/101
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 8/08 Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
• CPC Class Codes: G11C 8/10 Decoders
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H03K 19/215 using field-effect transistors
• CPC Class Codes: H03K 19/23 Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
• CPC Class Codes: H03K 3/35625 using complementary field-effect transistors
• CPC Class Codes: H03K 5/151 with two complementary outputs
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices

Abstract

Techniques for providing improved memory flip-flops and other logic circuits are described. A flip-flop uses only one p-channel transistor to drive the output node strongly to achieve fast results. To reduce diffusion area, parallel logic is substantially eliminated and only series branches are used, in critical areas. This allows all pull-up transistors and/or all pull-down transistors to be formed from contiguous active areas. The D-to-Q path is reduced, and the clock is used to control the output. The clock becomes the dominant controller of the output when it is located closest to the output. Placing the clock devices closest to the clocked nodes reduces clock skew. The rising D response time and falling D response time are caused to be as close as possible to reduce the overall cycle time. To reduce parasitics in the circuit, complex-gates are used which are asymmetric. Even multiples of series branches per gate are used to share contacts and eliminate breaks in the layout diffusion. Adding complex-gates to a circuit while using asymmetric gates for smaller layouts achieves additional functionality. One component of the clock, along with the master drive circuit, is used to drive the slave latch of a flip-flop to avoid inserting additional gates into the logic of the fast output path. Reset and set circuitry is designed to be outside the critical path of the clock, and outside the slave latch, to provide rapid Q output response time to the clock and D inputs.

Claims

1. A logic device formed on a semiconductor substrate for producing an output signal based on a plurality of input signals, the logic device comprising a first plurality of transistors of a first channel type, each of the first plurality of transistors coupled to a first supply node and a different node of at least three switchable nodes, for selectively pulling the switchable nodes to a first logic level based on the plurality of input signals, each of the switchable nodes forming a direct connection point between a drain of a transistor of the first channel type and a drain of a transistor of a second channel type, wherein all of the first plurality of transistors are formed using a first contiguous active area disposed within the semiconductor, wherein the first contiguous active area contains no permanently inactive transistors within the logic device.

2. A logic device as recited in claim 1, further comprising a second plurality of transistors of the second channel type, each of the second plurality of transistors coupled between a second supply node and a different node of said at least three switchable nodes, for selectively pulling the switchable nodes to a second logic level based on the plurality of input signals, the second plurality of transistors including at least three transistors of the second channel type, wherein all of the second plurality of transistors are formed using a second contiguous active area disposed within the semiconductor substrate, wherein the second contiguous active area contains no permanently inactive transistors that are within the logic device.

3. A logic device as recited in claim 1, wherein the logic device is a latch.

4. A logic device as recited in claim 1, wherein the logic device is a flip-flop.

5. A logic device as recited in claim 4, wherein the flip-flop has a set input or a reset input.

6. A logic device as recited in claim 4, wherein the flip-flop has a set input and a reset input.

7. A logic device as recited in claim 1, wherein the first plurality of transistors comprises at least four transistors, such that said at least three switchable nodes comprises at least four switchable nodes.

8. A logic device as recited in claim 1, wherein the first plurality of transistors comprises at least five transistors, such that said at least three switchable nodes comprises at least five switchable nodes.

9. A logic device as recited in claim 1, wherein the first plurality of transistors comprises at least six transistors, such that said at least three switchable nodes comprises at least six switchable nodes.

10. A logic device as recited in claim 1, wherein the first plurality of transistors comprises at least seven transistors, such that said at least three switchable nodes comprises at least seven switchable nodes.

11. A flip-flop formed on a semiconductor substrate for producing an output signal based on a plurality of input signals, the flip-flop comprising a first plurality of transistors of a first channel type, each of the first plurality of transistors coupled to a first supply node and a different node of at least three switchable nodes, for selectively pulling the switchable nodes to a first logic level based on the plurality of input signals, each of the switchable nodes forming a direct connection point between a drain of a transistor of the first channel type and a drain of a transistor of a second channel type, wherein all of the first plurality of transistors are formed using a first contiguous active area disposed within the semiconductor, wherein the first contiguous active area contains no permanently inactive transistors within the flip-flop.

12. A flip-flop as recited in claim 11, further comprising a second plurality of transistors of the second channel type, each of the second plurality of transistors coupled between a second supply node and a different node of said at least three switchable nodes, for selectively pulling the switchable nodes to a second logic level based on the plurality of input signals, the second plurality of transistors including at least three transistors of the second channel type, wherein all of the second plurality of transistors are formed using a second contiguous active area disposed within the semiconductor substrate, wherein the second contiguous active area contains no permanently inactive transistors that are within the flip-flop.

13. A flip-flop as recited in claim 12, wherein the first contiguous active area comprises a plurality of diffusion regions for forming the first plurality of transistors, wherein each of the plurality of diffusion regions that is configured to switch signal level is shared by exactly two active transistors of the first plurality of transistors.

14. A flip-flop as recited in claim 11, wherein the flip-flop is a static flip-flop.

15. A flip-flop as recited in claim 11, wherein the flip-flop is a dynamic flip-flop.

16. A flip-flop as recited in claim 11, wherein the flip-flop has a set input or a reset input.

17. A flip-flop as recited in claim 11, wherein the flip-flop has a set input and a reset input.

18. A flip-flop as recited in claim 11, wherein said at least three switchable nodes comprises at least four switchable nodes.

19. A flip-flop as recited in claim 11, wherein said at least three switchable nodes comprises at least five switchable nodes.

20. A flip-flop as recited in claim 11, wherein said at least three switchable nodes comprises at least six switchable nodes.

21. A flip-flop as recited in claim 11, wherein said at least three switchable nodes comprises at least seven switchable nodes.

22. A flip-flop formed on a semiconductor substrate for producing an output signal based on a plurality of input signals, the flip-flop comprising:

a first plurality of transistors of a first channel type, each of the first plurality of transistors coupled to a first supply node and a different node of at least three switchable nodes, for selectively pulling the switchable nodes to a first logic level based on the plurality of input signals, each of the switchable nodes forming a direct connection point between a drain of a transistor of the first channel type and a drain of a transistor of a second channel type, wherein all of the first plurality of transistors are formed using a first single contiguous active area disposed within the semiconductor, wherein the first contiguous active area contains no permanently inactive transistors within the flip-flop; and

a second plurality of transistors of a second channel type, each of the second plurality of transistors coupled between a second supply node and a different node of said at least three switchable nodes, for selectively pulling the switchable nodes to a second logic level based on the plurality of input signals, the second plurality of transistors including at least three transistors of the second channel type, wherein all of the second plurality of transistors are formed using a second single contiguous active area disposed within the semiconductor substrate.

23. A flip-flop as recited in claim 22, wherein the first contiguous active area comprises a plurality of diffusion regions for forming the first plurality of transistors, wherein each of the plurality of diffusion regions that is configured to switch signal level is shared by exactly two active transistors of the first plurality of transistors.

24. A flip-flop as recited in claim 22, wherein the flip-flop is a static flip-flop.

25. A flip-flop as recited in claim 22, wherein the flip-flop is a dynamic flip-flop.

26. A flip-flop as recited in claim 22, wherein the flip-flop has a set input or a reset input.

27. A flip-flop as recited in claim 22, wherein the flip-flop has a set input and a reset input.

28. A flip-flop as recited in claim 22, wherein said at least three switchable nodes comprises four switchable nodes.

29. A flip-flop as recited in claim 22, wherein said at least three switchable nodes comprises five switchable nodes.

30. A flip-flop as recited in claim 22, wherein said at least three switchable nodes comprises six switchable nodes.

31. A flip-flop as recited in claim 22, wherein said at least three switchable nodes comprises seven switchable nodes.

32. A logic circuit formed on a semiconductor, the logic circuit comprising:

a least three switchable nodes;

a first plurality of series transistor branches coupled between a first supply node and the switchable nodes for pulling the switchable nodes to a first logic level, wherein all of the first plurality of series transistor branches are disposed adjacent to each other in a first contiguous active area of the semiconductor; and

a second plurality of series transistor branches coupled between a second supply node and the switchable nodes for pulling the switchable nodes to a second logic level, wherein all of the second plurality of series transistor branches are disposed adjacent to each other on the semiconductor;

wherein at least one of the switchable nodes is coupled to an even number of said first plurality of series transistor branches and an even number of said second plurality of series transistor branches.

33. A logic circuit as recited in claim 32, wherein the second plurality of series transistor branches are disposed adjacent to each other in a second contiguous active area of the semiconductor.

34. A logic circuit as recited in claim 32, wherein two of the at least three switchable nodes are each coupled to an even number of said first plurality of series transistor branches and an even number of said second plurality of series transistor branches.

35. A logic circuit as recited in claim 32, wherein three of the at least three switchable nodes are each coupled to an even number of said first plurality of series transistor branches and an even number of said second plurality of series transistor branches.

36. A logic circuit as recited in claim 32, wherein said at least three switchable nodes comprises at least four switchable nodes, each of which is coupled to an even number of said first plurality of series transistor branches and an even number of said second plurality of series transistor branches.

37. A logic circuit as recited in claim 32, wherein said at least three switchable nodes comprises at least five switchable nodes, each of which is coupled to an even number of said first plurality of series transistor branches and an even number of said second plurality of series transistor branches.

38. A logic circuit as recited in claim 32, wherein said at least three switchable nodes comprises at least six switchable nodes, each of which is coupled to an even number of said first plurality of series transistor branches and an even number of said second plurality of series transistor branches.

39. A logic circuit as recited in claim 32, wherein said at least three switchable nodes comprises at least seven switchable nodes, each of which is coupled to an even number of said first plurality of series transistor branches and an even number of said second plurality of series transistor branches.

40. A logic circuit formed on a semiconductor substrate for producing an output signal based on a plurality of input signals, the logic circuit comprising:

a first plurality of transistors of a first channel type, each of the first plurality of transistors coupled to a first supply node and a different node of at least three switchable nodes, for selectively pulling the switchable nodes to a first logic level based on the plurality of input signals, each of the switchable nodes forming a direct connection point between a transistor of the first channel type and a transistor of a second channel type; and

a second plurality of transistors of the second channel type, each of the second plurality of transistors coupled between a second supply node and a different node of said at least three switchable nodes, for selectively pulling the switchable nodes to a second logic level based on the plurality of input signals, the second plurality of transistors including at least three transistors of the second channel type, wherein all of the second plurality of transistors are formed using a single contiguous active area disposed within the semiconductor substrate.

41. A method of designing a logic circuit, the method comprising:

generating a first logic function to represent a pull-down network of the logic circuit, the pull-down network for pulling an output node down to a first logic level in response to a first predetermined combination of inputs, wherein said generating the first logic function includes using a symbolic representation corresponding to a Karnaugh map, the symbolic representation including a plurality of values representing logic ones and logic zeros, to generate the first logic function directly from the logic zeros in the symbolic representation;

generating a second logic function to represent a pull-up network of the logic circuit, the pull-up network for pulling the output node up to a second logic level in response to a second predetermined combination of inputs, wherein said generating the second logic function includes using the symbolic representation to generate the second logic function directly from the logic ones in the symbolic representation; and

designing the logic circuit to include the pull-down network and the pull-up network in accordance with the first logic function and the second logic function, respectively.

42. A logic circuit comprising:

a pull-down network including a plurality of n-channel transistors configured to pull an output node down to a first logic level corresponding to a first supply node in response to a first predetermined combination of inputs, the pull-down network embodying a first logic function, wherein the pull-down network includes one or more series-only transistor branches with no series-parallel transistor branches connected between the output node and the first supply node; and

a pull-up network including a plurality of p-channel transistors configured to pull the output node up to a second logic level corresponding to a second supply node in response to a second predetermined combination of inputs, the pull-up network embodying a second logic function which is a transistor-minimized logic complement of the first logic function, wherein the pull-up network includes one or more series-only transistor branches with no series-parallel transistor branches connected between the output node and the second supply node.

43. A logic circuit as recited in claim 42, wherein the logic circuit is a flip-flop.

44. A logic circuit as recited in claim 42, wherein the logic circuit is a multiplexer.

45. A logic circuit as recited in claim 44, wherein the multiplexer includes three selectable inputs.

46. A logic circuit as recited in claim 42, wherein the logic circuit is an adder.

47. A logic circuit as recited in claim 42, wherein the logic circuit is a majority gate.

48. A logic circuit as recited in claim 42, wherein the logic circuit is not a gate-array type of logic circuit.