Methods and apparatus for noise shaping a mixed signal power output

• US 6,297,697 B2
• Filed: 01/11/2001
• Issued: 10/02/2001
• Est. Priority Date: 03/09/1999
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: Tripath Technology, Inc. (Cloudward, Inc.)
• Inventors: Tripathi, Adya S., Delano, Cary L.
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): Nguyen, Patricia T.
• Application Number:
  US09/759,005
• Publication Number:
  US 20010001547A1
• Time in Patent Office: 264 Days
• Field of Search: 330/107, 330/109, 330/51, 330/124.R, 330/10, 330/251, 330/207.A, 330/294, 330/302, 330/306
• US Class Current: 330/207.00A
• CPC Class Codes: H03F 2200/331 Sigma delta modulation being used in an amplifying circuit
• CPC Class Codes: H03F 3/217 Class D power amplifiers; Switching amplifiers
• CPC Class Codes: H03F 3/2171 with field-effect devices H03F3/2173 - H03F3/2178 take precedence
• CPC Class Codes: H03F 3/2175 using analogue-digital or digital-analogue conversion H03F3/2173 takes precedence
• CPC Class Codes: H03F 3/72 Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal

Abstract

A signal processing circuit and method for processing an input signal are described. The circuit includes a frequency selective network, an amplification stage, and at least one continuous-time feedback path from the output of the amplification stage to the frequency selective network. The amplification stage includes a switching amplifier and an analog amplifier. Switching circuitry alternately enables the switching and analog amplifiers for processing of the input signal.

Claims

1. A signal processing circuit for processing an input signal, comprising:

a frequency selective network;

an amplification stage coupled to the frequency selective network, the amplification stage comprising a switching amplifier, an analog amplifier, and an output terminal;

at least one continuous-time feedback path from the output terminal of the amplification stage to the frequency selective network; and

switching circuitry for alternately enabling the switching and analog amplifiers for processing of the input signal, the switching circuitry comprising level detection circuitry for monitoring a signal level indicative of the input signal, and wherein the switching circuitry is configured to alternately enable the switching and analog amplifiers in response to the signal level such that where the signal level is below a first threshold level the input signal is processed with the analog amplifier, and where the signal level is above the first threshold level the input signal is processed with the switching amplifier.

2. The signal processing circuit of claim 1 wherein the first threshold level is associated with a quiescence region for the signal processing circuit.

3. The signal processing circuit of claim 1 wherein the switching circuitry is further configured to alternately enable the switching and analog amplifiers in response to the signal level such that where the signal level exceeds a second threshold level the input signal is processed with the analog amplifier, and where the signal level is between the first and second thresholds the input signal is processed with the switching amplifier.

4. The signal processing circuit of claim 3 wherein the second threshold level is associated with a power supply rail associated with the signal processing circuit.

5. The signal processing circuit of claim 1 wherein the amplification stage is configured for base band operation and the frequency selective network comprises at least one integrator stage.

6. The signal processing circuit of claim 5 wherein the amplification stage is configured for audio amplification.

7. The signal processing circuit of claim 1 wherein the amplification stage is configured for band pass operation and the frequency selective network comprises at least one resonator stage.

8. The signal processing circuitry of claim 1 wherein the switching circuitry further comprises force mode circuitry for forcing use of one of the switching amplifier and analog amplifier regardless of the signal level.

9. The signal processing circuitry of claim 8 wherein the force mode circuitry forces use of the switching amplifier regardless of the signal level in a first mode, forces use of the analog amplifier regardless of the signal level in a second mode, and allows alternate enablement of the switching and analog amplifier in response to the signal level in a third mode.

10. The signal processing circuitry of claim 1 wherein the level detection circuitry is configured to monitor the signal level at a node associated with the frequency selective network.

11. The signal processing circuitry of claim 1 wherein the level detection circuitry is configured to monitor the signal level at a node associated with the amplification stage.

12. The signal processing circuitry of claim 1 wherein the level detection circuitry is configured to monitor the signal level at a node associated with the at least one continuous-time feedback path.

13. The signal processing circuitry of claim 1 wherein the frequency selective network is configured to push transition distortion associated with alternate enablement of the switching and analog amplifiers out of a band of operation of the signal processing circuit.

27. An electronic device including the signal processing circuit of claim 1.

14. A signal processing circuit for processing an input signal, comprising:

a frequency selective network;

an amplification stage coupled to the frequency selective network, the amplification stage comprising a switching amplifier, an analog amplifier, and an output terminal;

at least one continuous-time feedback path from the output terminal of the amplification stage to the frequency selective network; and

switching circuitry for alternately enabling the switching and analog amplifiers for processing of the input signal, the switching circuitry comprising level detection circuitry for monitoring a signal level indicative of the input signal, and wherein the switching circuitry is configured to alternately enable the switching and analog amplifiers in response to the signal level such that where the signal level is above a first threshold level the input signal is processed with the analog amplifier, and where the signal level is below the first threshold level the input signal is processed with the switching amplifier.

15. The signal processing circuit of claim 14 wherein the first threshold level is associated with a power supply rail associated with the signal processing circuit.

16. The signal processing circuit of claim 14 wherein the switching circuitry is further configured to alternately enable the switching and analog amplifiers in response to the signal level such that where the signal level is below a second threshold level the input signal is processed with the analog amplifier, and where the signal level is between the first and second thresholds the input signal is processed with the switching amplifier.

17. The signal processing circuit of claim 16 wherein the second threshold level is associated with a quiescence region for the signal processing circuit.

18. The signal processing circuit of claim 14 wherein the amplification stage is configured for base band operation and the frequency selective network comprises at least one integrator stage.

19. The signal processing circuit of claim 18 wherein the amplification stage is configured for audio amplification.

20. The signal processing circuit of claim 14 wherein the amplification stage is configured for band pass operation and the frequency selective network comprises at least one resonator stage.

21. The signal processing circuitry of claim 14 wherein the switching circuitry further comprises force mode circuitry for forcing use of one of the switching amplifier and analog amplifier regardless of the signal level.

22. The signal processing circuitry of claim 21 wherein the force mode circuitry forces use of the switching amplifier regardless of the signal level in a first mode, forces use of the analog amplifier regardless of the signal level in a second mode, and allows alternate enablement of the switching and analog amplifier in response to the signal level in a third mode.

23. The signal processing circuitry of claim 14 wherein the level detection circuitry is configured to monitor the signal level at a node associated with the frequency selective network.

24. The signal processing circuitry of claim 14 wherein the level detection circuitry is configured to monitor the signal level at a node associated with the amplification stage.

25. The signal processing circuitry of claim 14 wherein the level detection circuitry is configured to monitor the signal level at a node associated with the at least one continuous-time feedback path.

26. The signal processing circuitry of claim 14 wherein the frequency selective network is configured to push transition distortion associated with alternate enablement of the switching and analog amplifiers out of a band of operation of the signal processing circuit.

28. An electronic device including the signal processing circuit of claim 14.