Low-voltage joystick port interface
DCFirst Claim
1. An interface between a joystick device having a first source voltage and a processor, comprising:
- a Resistor-Capacitor (RC) network, connected to the joystick device, said RC network having a capacitor that generates an analog joystick position measurement signal; and
an interface circuit having a second source voltage that is lower than the first source voltage, including a buffer circuit, in a first operation mode of said interface, receiving said analog joystick position measurement signal, outputting a first logic state as a digital signal before said analog joystick measurement signal exceeds said predetermined threshold, and outputting a second logic state as said digital signal after said analog joystick measurement signal exceeds said predetermined threshold; and
a pulse generator generating a pulse based on said digital signal in said first operation mode of said interface, a width of said pulse representing a coordinate position of said joystick device, the capacitance value of said capacitor being a function of said predetermined threshold that prevents deviation of the width of said pulse from expected values.
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Abstract
The joystick port interface includes an integrated circuit receiving an analog joystick position measurement signal and outputting a digital pulse signal to a processor which signifies a joystick coordinate value. The integrated circuit includes a pulse generator and a bidirectional buffer circuit. The bidirectional buffer circuit receives the analog joystick position measurement signal and selectively discharges an RC network capacitor which provides this analog measurement. This implementation provides a joystick port which uses low-voltage CMOS VLSI structures which can interface a conventional high-voltage joystick with the processor.
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Citations
19 Claims
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1. An interface between a joystick device having a first source voltage and a processor, comprising:
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a Resistor-Capacitor (RC) network, connected to the joystick device, said RC network having a capacitor that generates an analog joystick position measurement signal; and
an interface circuit having a second source voltage that is lower than the first source voltage, including a buffer circuit, in a first operation mode of said interface, receiving said analog joystick position measurement signal, outputting a first logic state as a digital signal before said analog joystick measurement signal exceeds said predetermined threshold, and outputting a second logic state as said digital signal after said analog joystick measurement signal exceeds said predetermined threshold; and
a pulse generator generating a pulse based on said digital signal in said first operation mode of said interface, a width of said pulse representing a coordinate position of said joystick device, the capacitance value of said capacitor being a function of said predetermined threshold that prevents deviation of the width of said pulse from expected values. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
where Cnew represents the capacitance of the RC network capacitor, and Vtnew represents said predetermined threshold.
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9. A processor based system, comprising:
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a processor;
a joystick device having a first source voltage; and
an interface interfacing said joystick device with said processor, said interface including, a Resistor-Capacitor (RC) network, connected to the joystick device, said RC network having a capacitor that generates an analog joystick position measurement signal; and
an interface circuit having a second source voltage that is lower than the first source voltage, including a buffer circuit, in a first operation mode of said interface, receiving said analog joystick position measurement signal, outputting a first logic state as a digital signal before said analog joystick measurement signal exceeds said predetermined threshold, and outputting a second logic state as said digital signal after said analog joystick measurement signal exceeds said predetermined threshold, and a pulse generator generating a pulse based on said digital signal in said first operation mode of said interface, a width of said pulse representing a coordinate position of said joystick device, and outputting said pulse to said processor, wherein the capacitance value of said capacitor is a function of said predetermined threshold that prevents deviation of the width of said pulse from expected values. - View Dependent Claims (10, 11, 12, 13)
where Cnew represents the capacitance of the RC network capacitor, and Vtnew represents said predetermined threshold.
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14. A method of interfacing a joystick device having a first source voltage with a processor, comprising:
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(a) receiving an analog joystick measurement signal from a Resistor-Capacitor (RC) network connected to the joystick device, said RC network having a capacitor that generates said analog joystick measurement signal;
(b) generating a digital signal, the logic level of said digital signal being set based on whether said analog joystick measurement signal exceeds a predetermined threshold level, said digital signal being generated by an interface circuit having a second source voltage that is lower than the first source voltage;
(c) outputting said digital signal to a pulse generator;
(d) generating a pulse based on the logic level of said first digital signal, a width of said pulse representing a coordinate position of said joystick device; and
(e) outputting said pulse to said processor, wherein the capacitance value of said capacitor is a function of said predetermined threshold level that prevents deviation of the width of said pulse from expected values. - View Dependent Claims (15, 16, 17, 18, 19)
said steps (a)-(e) are performed in a first mode of operation; and further including, (f) placing said capacitor in a discharged state in a second mode of operation.
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16. The method of claim 15, further comprising:
(g) permitting said charge storage device to begin charging in said first mode of operation.
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17. The method of claim 15, further comprising:
(g) prohibiting said steps (d) and (e) in response to a control signal from said processor in said second mode of operation.
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18. The method of claim 14, further comprising:
(f) prohibiting said steps (d) and (e) in response to a control signal from said processor.
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19. The method of claim 14, wherein the capacitance value of said capacitor satisfies the formula:
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where Cnew represents the capacitance of the RC network capacitor, and Vtnew represents said predetermined threshold level.
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Specification