Method and apparatus for memory access scheduling in a video graphics system

• US 6,297,832 B1
• Filed: 01/04/1999
• Issued: 10/02/2001
• Est. Priority Date: 01/04/1999
• Status: Expired due to Term

• Current Assignee: ATI Technologies ULC (Advanced Micro Devices, Inc.)
• Original Assignee: ATI International SRL (Advanced Micro Devices, Inc.)
• Inventors: Wang, Chun, Chow, Paul, Swan, Philip L., Mizuyabu, Carl K.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US09/224,692
• Time in Patent Office: 1,002 Days
• Field of Search: 345/531-535, 345/540, 345/502, 345/501, 345/569, 345/555, 711/5, 711/100, 711/154, 711/157, 711/158, 711/170, 711/173
• US Class Current: 345/540
• CPC Class Codes: G06T 1/60 Memory management
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 2360/12 Frame memory handling
• CPC Class Codes: G09G 2360/122 Tiling
• CPC Class Codes: G09G 2360/123 using interleaving
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A method and apparatus for sequencing memory accesses in a video graphics system such that page faults are effectively hidden is accomplished by receiving a memory access request from one of a plurality of clients, where the plurality of clients includes both linear clients and tiled memory clients. The clients access data stored in a memory that includes at least two banks. Once the memory request has been received, it is evaluated based on other pending requests in order to determine the optimal ordering pattern for execution of the memory requests. The optimal ordering pattern typically includes sequencing alternating accesses between the two banks of the memory such that when a page fault is occurring in one bank of the memory, a memory access is occurring in the opposing bank. Once the ordering of the memory requests has been performed, the requests are executed.

Claims

1. A video graphics circuit comprising:

a memory having at least a first bank and a second bank;

at least one linear memory client, wherein linear memory clients store and retrieve data stored in the memory in a linear format

at least one tiled memory client, wherein tiled memory clients store and retrieve data stored in the memory in a tiled format; and

a memory controller operably coupled to the memory, the linear memory client, and the tiled memory client,

wherein when the memory controller receives a set of data from linear memory clients to store in the memory, the memory controller stores the set of linear data in the memory in a burst interleaved format such that successive portions of the set of linear data are stored in alternating banks of the memory, wherein size of the successive portions is determined based on a page fault time,

wherein when the memory controller receives a set of data from tiled memory clients to store in the memory, the memory controller stores the set of tiled data in the memory in a tiled format such that successive tiles of the set of tiled data are stored in alternating banks of the memory, wherein a dimension of the tiles is determined based on the page fault time,

wherein when the memory controller receives a request to retrieve data from linear clients and from tiled clients, the memory controller structures reads from the memory such that page faults are hidden.

2. The video graphics circuit of claim 1, wherein the memory controller untiles tiled data read from the memory and provides it to tiled memory clients in a non-tiled format.

3. The video graphics circuit of claim 1, wherein the at least one tiled memory client includes a video image processor, wherein the video image processor stores and retrieves tiled data that includes a tiled representation of a video image.

4. The video graphics circuit of claim 3, wherein the video image processor further comprises an MPEG decoder, wherein the MPEG decoder stores and retrieves MPEG video data.

5. The video graphics circuit of claim 1 further comprises at least one combination memory client, wherein combination memory clients store and retrieve linear and tiled data using the memory controller.

6. The video graphics circuit of claim 5, wherein the at least one combination memory client includes a graphics image processor that generates graphics images that the graphics image processor stores and retrieves image data using the memory controller.

7. The video graphics circuit of claim 1, wherein the at least one tiled memory client includes a video display engine, wherein the video display engine reads tiled data using the memory controller, wherein the video display engine generates a video display signal.

8. The video graphics circuit of claim 1, wherein the at least one linear memory client includes a graphics display engine, wherein the graphics display engine reads linear data using the memory controller, wherein the graphics display engine generates a graphics display signal.

9. The video graphics circuit of claim 1, wherein the memory controller further comprises:

a scheduler, wherein the scheduler receives memory access requests from linear and tiled clients, and wherein the scheduler determines ordering of the memory access requests; and

a sequencer operably coupled to the scheduler, wherein the sequencer issues memory commands to the memory based on the memory access requests.

10. The video graphics circuit of claim 9, wherein the scheduler breaks up selected memory access requests into smaller requests, wherein the scheduler determines ordering of the memory access requests such that smaller requests of a selected memory access request are performed non-sequentially.

11. The video graphics circuit of claim 9, wherein the scheduler interleaves tiled memory access requests with linear memory access requests to minimize timing penalties associated with page faults.

12. The video graphics circuit of claim 1, wherein the memory is a two-bank synchronous dynamic random access memory, wherein during a memory access to the first bank, preparation for a subsequent second bank access occurs, and wherein during a memory access to the second bank, preparation for a subsequent first bank access occurs.

13. A method for memory control comprising:

receiving a plurality of memory access requests from a plurality of memory clients, wherein each of the plurality of memory clients accesses a memory, wherein the memory includes at least a first bank and a second bank;

performing the plurality of memory access requests in a sequence that minimizes penalties associated with page faults,

wherein store memory access requests from linear clients of the plurality of clients are performed in such a way that linear data from the linear clients are stored in the memory in a burst interleaved format such that successive portions of the linear data are stored in alternating banks of the memory, wherein the size of the successive portions is determined based on a page fault time,

wherein store memory access requests from tiled memory clients of the plurality of clients are performed in such a way that tiled data from the tiled clients is stored in the memory in a tiled format such that successive tiles of the tiled data are stored in alternating banks of the memory, wherein a dimension of the tiles is determined based on the page fault time,

wherein retrieve memory access requests are performed such that data stored in the memory is presented to the plurality of clients in a format that matches a format corresponding to store memory access requests received from each of the plurality of clients.

14. The method of claim 13, wherein performing further comprises ordering execution of memory access requests such that accesses to the first bank of the memory preferably follow accesses to the second bank of the memory and such that access to the second bank of the memory preferably follow accesses to the first bank of the memory.

15. The method of claim 14, wherein ordering execution of memory access requests further comprises ordering execution of memory access requests such that a page fault in one bank of the memory is hidden by a memory access to another bank of the memory.

16. The method of claim 15, wherein performing further comprises dividing accesses of memory access requests into access portions, wherein execution of access portions of memory access requests are ordered in a non-sequential manner in order to minimize the penalties associated with page faults.

17. The method of claim 13, wherein receiving a plurality of memory access requests from a plurality of memory clients, further comprises receiving a plurality of memory access requests from a plurality of memory clients in a video graphics system, wherein the plurality of memory clients includes a display output engine, a video image processor, and a graphics processor.

18. A memory controlling circuit comprising:

a memory having a first bank and a second bank, wherein the memory stores linear data in a burst interleaved format, wherein the burst interleaved format stores successive portions of the linear data in alternating banks of the memory, wherein size of the successive portions is determined based on a page fault time;

a client that performs linear memory accesses; and

a memory controller operably coupled to the memory and the client, wherein the memory controller receives requests from the client and accesses the memory based on the requests, wherein the memory controller determines ordering of the memory access requests such that smaller requests of a selected memory access request are performed non-sequentially.

19. The memory controlling circuit of claim 18, wherein the client is a graphics display engine, and wherein the linear data includes graphics data, wherein the graphics display engine reads the graphics data from the memory using the memory controller, and wherein the graphics display engine produces a display output signal based on the graphics data.

20. The memory controlling circuit of claim 18, wherein the memory is a two-bank synchronous dynamic random access memory, wherein during a memory access to the first bank, preparation for a subsequent second bank access occurs, and wherein during a memory access to the second bank, preparation for a subsequent first bank access occurs.