Applications for non-volatile memory cells

• US 6,297,989 B1
• Filed: 02/26/1999
• Issued: 10/02/2001
• Est. Priority Date: 02/26/1999
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Noble, Wendell P., Cloud, Eugene H.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US09/261,597
• Time in Patent Office: 949 Days
• Field of Search: 365/185.08, 365/185.05, 365/185.18, 365/149, 365/145, 365/185.09
• US Class Current: 365/185.08
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Additional applications for DRAM technology compatible non-volatile memory cells are presented. The novel applications include the integration of DRAM technology compatible non-volatile memory cells which can be fabricated on a DRAM chip with little or no modification of the DRAM optimized process flow. The novel applications of DRAM technology compatible non-volatile memory cells operate with lower programming voltages than that used by conventional non-volatile memory cells, yet still hold sufficient charge to withstand the effects of parasitic capacitances and noise due to circuit operation. Hence, the requirements of low power densely packed integrated circuits is realized for smaller, portable microprocessor devices.

An example of one such application includes a circuit switch. The circuit switch has a non-volatile memory cell which a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate, a capacitor, and a vertical electrical via coupling a bottom plate of the capacitor through an insulator layer to a gate of MOSFET. A wordline is coupled to a top plate of the capacitor in the non-volatile memory cell. A sourceline is coupled to a source region of the MOSFET in the non-volatile memory cell. A bit line is coupled to a drain region of the MOSFET in the non-volatile memory cell and coupled to a logic/select circuit.

Another example of an application includes a shadow random access memory (RAM) cell. The shadow RAM cell has a non-volatile memory cell with the structure described above. Circuit arrays and electronic systems which incorporate these novel applications are included with the scope of this invention. Likewise, methods for forming and operating these novel device applications are provided.

Claims

1. A circuit switch, comprising:

a non-volatile memory cell, wherein the non-volatile memory cell includes;

a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;

a capacitor, wherein the capacitor includes a stacked capacitor formed in a subsequent layer above the MOSFET according to a dynamic random access memory (DRAM) process flow, and wherein a bottom plate of the stacked capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate; and

a vertical electrical via coupling a bottom plate of the capacitor through an insulator layer to a gate of the MOSFET;

a wordline coupled to a top plate of the capacitor in the non-volatile memory cell;

a sourceline coupled to a source region of the MOSFET in the non-volatile memory cell; and

a bit line coupled to a drain region of the MOSFET in the non-volatile memory cell and coupled to logic/select circuit.

2. The circuit switch of claim 1, wherein the MOSFET includes an n-channel metal oxide semiconductor (NMOS) transistor.

3. The circuit switch of claim 1, wherein the non-volatile memory cell includes a FLASH memory cell.

4. The circuit switch of claim 1, wherein the logic/select circuit couples to a multiplexor which couples a first circuit line to a second circuit line when the non-volatile memory cell is in a first programmed state, and wherein the multiplexor decouples the first circuit line from the second circuit line when the non-volatile memory cell is in a second programmed state.

5. A circuit switch array, comprising:

a number of non-volatile memory cells, wherein each non-volatile memory cell includes;

a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;

a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer, and wherein a bottom plate of the stacked capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate; and

an electrical contact coupling a bottom plate of the stacked capacitor through the insulator layer to a gate of the MOSFET;

a control line coupled to the capacitor in the number of non-volatile memory cells;

a sourceline coupled to a source region of the MOSFET in the number of non-volatile memory cells; and

a bit line coupled to a drain region of the MOSFET in the number of non-volatile memory cells and coupled to a multiplexor which couples a number of input circuit lines to a number of output circuit lines.

6. The circuit switch array of claim 5, wherein the bit line couples to the multiplexor through a logic select circuit.

7. The circuit switch array of claim 6, wherein the multiplexor couples an input circuit line to a first one of the output circuit lines when a non-volatile memory cell is in a first programmed state, and wherein the multiplexor couples the input circuit line to a second one of the output circuit lines when the non-volatile memory cell is in a second programmed state.

8. The circuit switch array of claim 6, wherein, multiplexor couples a first set of the number of input circuit lines to a first set of the number of output circuit lines when a non-volatile memory cell is in a first programmed state, and wherein the multiplexor couples the first set of the number of input circuit lines to a second set of the number of output circuit lines when the non-volatile memory cell is in a second programmed state.

9. The circuit switch array of claim 5, wherein the number of output circuit lines include a number of redundant output circuit lines.

10. The circuit switch array of claim 9, wherein the number of redundant output circuit lines include a number of redundant DRAM wordlines.

11. The circuit switch array of claim 5, wherein the electrical contact includes a polysilicon plug.

12. The circuit repair array of claim 5, wherein the circuit switch array is formed on a DRAM chip.

13. An electronic system, comprising:

a processor;

a dynamic random access memory (DRAM) chip; and

a system bus coupling the processor to the DRAM chip, wherein the DRAM chip includes a circuit switch, and wherein the circuit switch includes;

a non-volatile memory cell, wherein the non-volatile memory cell includes;

a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;

a stacked capacitor formed according to a DRAM process flow, wherein a bottom plate of the stacked capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate; and

a vertical electrical via coupling a bottom plate of the stacked capacitor through an insulator layer to a gate of MOSFET;

a wordline coupled to a top plate of the capacitor in the non-volatile memory cell;

a sourceline coupled to a source region of the MOSFET in the non-volatile memory cell; and

a bit line coupled to a drain region of the MOSFET in the non-volatile memory cell and coupled to logic/select circuit.

14. The electronic system of claim 13, wherein the non-volatile memory cell includes an electronically erasable and programmable read only memory (EEPROM) cell.

15. The electronic system of claim 13, wherein the logic/select circuit couples to a multiplexor which couples a first circuit line to a second circuit line when the non-volatile memory cell is in a first programmed state, and wherein the multiplexor decouples the first circuit line from the second circuit line when the non-volatile memory cell is in a second programmed state.

16. The electronic system of claim 15, wherein the second circuit line is a redundant DRAM row line or a redundant DRAM column line.

17. A method for operating a switch on a DRAM chip, comprising:

programming a non-volatile memory cell to either a first or second programmed state, wherein the non-volatile memory cell includes;

a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;

a capacitor formed according to a DRAM process flow, wherein a bottom plate of the stacked capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate; and

a vertical electrical via coupling a bottom plate of the capacitor through an insulator layer to a gate of MOSFET; and

passing the first or second programmed state from the non-volatile memory cell to a logic/select circuit, wherein passing the first or second to the logic/select circuit includes causing a multiplexor associated with the non-volatile memory cell to couple a first circuit line to a second circuit line when the non-volatile memory cell is in a first programmed state, and includes causing the multiplexor decouple the first circuit line from the second circuit line when the non-volatile memory cell is in a second programmed state.

18. A method for replacing inoperable circuit lines on a DRAM chip, comprising:

reading a state information of a number of non-volatile memory cells, wherein each non-volatile memory cell includes;

a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;

a stacked capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer, wherein a bottom plate of the stacked capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate; and

an electrical contact coupling a bottom plate of the stacked capacitor through the insulator layer to a gate of MOSFET;

passing the state information of the non-volatile memory cell to a multiplexor, wherein passing the state information to the multiplexor includes causing the multiplexor to switch the coupling of an input circuit line from a first output circuit line to a second circuit line.

19. The method of claim 18, wherein passing the state information to the multiplexor includes passing the state information to the multiplexor through a logic/select circuit.

20. The method of claim 18, wherein the method further includes programming at least one of the non-volatile memory cells to a first programmed state after testing an integrated circuit die.

21. The method of claim 18, wherein causing the multiplexor to switch the coupling of the input circuit line includes causing the multiplexor to switch the coupling of the input circuit line when the non-volatile memory cell is in a first programmed state.

22. The method of claim 18, wherein causing the multiplexor to switch the coupling of the input circuit line from a first output circuit line to a second circuit line includes causing the multiplexor to switch the coupling of the input circuit line to a redundant circuit line.

23. A shadow random access memory (RAM) cell, comprising:

a non-volatile memory cell, wherein the non-volatile memory cell includes;

a first metal oxide semiconductor field effect transistor (MOSFET) formed in a substrate;

a first capacitor, wherein a bottom plate of the first capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate; and

a vertical electrical via coupling a bottom plate of the first capacitor through an insulator layer to a gate of first MOSFET; and

a dynamic random access memory (DRAM) cell including a second MOSFET and a second capacitor, wherein a first diffused region is shared between the first MOSFET and the second MOSFET.

24. The shadow RAM cell of claim 23, wherein the second capacitor is a stacked capacitor and is coupled to the first diffused region.

25. The shadow RAM cell of claim 23, wherein the first capacitor includes a stacked capacitor formed in a subsequent layer above the first MOSFET according to a dynamic random access memory (DRAM) process flow.

26. The shadow RAM cell of claim 23, wherein the non-volatile memory cell includes an electronically erasable and programmable read only memory (EEPROM) cell.

27. The shadow RAM cell of claim 23, wherein the first MOSFET includes an n-channel metal oxide semiconductor (NMOS) transistor.

28. An array of shadow RAM cells, comprising:

a number of non-volatile memory cells, wherein each non-volatile memory cell includes;

a metal oxide semiconductor field effect transistor (MOSFET) formed in a semiconductor substrate;

a first capacitor formed according to a dynamic random access memory (DRAM) process in a subsequent layer above the MOSFET and separated from the MOSFET by an insulator layer, wherein a bottom plate of the first capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate; and

an electrical contact coupling a bottom plate of the first capacitor through the insulator layer to a gate of the MOSFET;

a number of dynamic random access memory (DRAM) cells, wherein each DRAM cell includes a second MOSFET and a second capacitor coupled to a first diffused region for the second MOSFET, and wherein a first diffused region is shared between the first MOSFET and the second MOSFET;

a control line coupled to a top plate of the first capacitor in the number of non-volatile memory cells;

a first group of bit lines coupled to a second diffused region of the first MOSFET in the number of non-volatile memory cells; and

a second group of bit lines coupled to a second diffused region of the second MOSFET in the number of DRAM cells.

29. The array of shadow RAM cells of claim 28, wherein the second capacitor is a stacked capacitor.

30. The array of shadow RAM cells of claim 28, wherein the second capacitor includes a stacked capacitor formed in a subsequent layer above the first MOSFET according to a dynamic random access memory (DRAM) process flow.

31. The array of shadow RAM cells of claim 28, wherein the capacitor dielectric is conformal to the bottom plate, and wherein the top plate is conformal to the capacitor dielectric, a portion of the top plate being located within the interior walls of the bottom plate.

32. The array of shadow RAM cells of claim 28, wherein the non-volatile memory cell includes an electronically erasable and programmable read only memory (EEPROM) cell.

33. The array of shadow RAM cells of claim 28, wherein array of shadow RAM cells includes a serial numbering device.

34. An electronic system, comprising:

a processor;

a dynamic random access memory (DRAM) chip; and

a system bus coupling the processor to the DRAM chip, wherein the DRAM chip includes a shadow random access memory (RAM) cell, and wherein each shadow random access memory (RAM) cell includes;

a non-volatile memory cell, wherein the non-volatile memory cell includes;

a first metal oxide semiconductor field effect transistor (MOSFET) formed in a substrate;

a first capacitor, wherein a bottom plate of the first capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate; and

a vertical electrical via coupling a bottom plate of the first capacitor through an insulator layer to a gate of the first MOSFET; and

a dynamic random access memory (DRAM) cell including a second MOSFET and a second capacitor, wherein a first diffused region is shared between the first MOSFET and the second MOSFET.

35. The electronic system of claim 34, wherein the second capacitor is a stacked capacitor and is coupled to the first diffused region.

36. The electronic system of claim 34, wherein the first capacitor includes a stacked capacitor formed in a subsequent layer above the first MOSFET according to a dynamic random access memory (DRAM) process flow.

37. The electronic system of claim 34, wherein the capacitor dielectric is conformal to the bottom plate, and wherein the top plate is conformal to the capacitor dielectric, a portion of the top plate being located within the interior walls of the bottom plate.

38. The electronic system of claim 34, wherein the non-volatile memory cell includes an electronically erasable and programmable read only memory (EEPROM) cell.

39. The electronic system of claim 34, wherein array of shadow RAM cells includes a beginning input/output system (BIOS).

40. A method for storing data in an electronic system, comprising:

sharing a first diffused region between a non-volatile memory cell and a dynamic random access memory cell formed in a semiconductor substrate, wherein the non-volatile memory cell includes;

a first metal oxide semiconductor field effect transistor (MOSFET) formed in a substrate;

a first capacitor, wherein a bottom plate of the first capacitor is cup shaped having interior walls and exterior walls and is separated by a capacitor dielectric from a top plate; and

a vertical electrical via coupling a bottom plate of the first capacitor through an insulator layer to a gate of the first MOSFET, and wherein the DRAM cell includes a second MOSFET and a second capacitor; and

transferring a charge from the second capacitor to the first capacitor during a power down mode of the electronic system.