Incremental compilation of electronic design for work group

• US 6,298,319 B1
• Filed: 08/26/1999
• Issued: 10/02/2001
• Est. Priority Date: 10/28/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Fairbanks, Brent A., Heile, Francis B.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US09/383,479
• Time in Patent Office: 768 Days
• Field of Search: 703/20, 703/26, 703/27, 716/17, 717/6, 709/232, 709/215
• US Class Current: 703/26
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/318516 Test of programmable logic devices [PLDs]
• CPC Class Codes: G06F 11/0748 in a remote unit communicating with a single-box computer node experiencing an error/fault remote testing G06F11/2294
• CPC Class Codes: G06F 11/2294 by remote test
• CPC Class Codes: G06F 2111/02 CAD in a network environment, e.g. collaborative CAD or distributed simulation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/3308 using simulation
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 8/60 Software deployment
• CPC Class Codes: G06F 8/65 Updates security arrangements therefor G06F21/57
• CPC Class Codes: G06F 8/71 Version control security arrangements therefor G06F21/57; Configuration management
• CPC Class Codes: G06Q 10/06 Resources, workflows, human or project management; Enterprise or organisation planning; Enterprise or organisation modelling
• CPC Class Codes: G06Q 10/10 Office automation; Time management
• CPC Class Codes: Y10S 707/99953 Recoverability
• CPC Class Codes: Y10S 707/99954 Version management

Abstract

A work group computing system for facilitating programmable logic device design among multiple engineers has a global work space including design project source files, a compilation basis, a compilation report text file, a binary assignments database and a user-readable assignments text file. Any number of local work spaces contain downloaded versions of any of the project source files, local compilation processing results for that user and a local assignment database containing records of downloaded assignments. Downloaded project source files or assignments are assigned states by the user such as default, locked, owned-write, owned-read only to facilitate coordination amongst the user engineers. The system controls editing of files so that two engineers may not inadvertently edit the same global source file at the same time. Individual engineers receive automatic updates of new versions of source files; files that are being edited are locked, and an isolation mode allows an engineer to work with source files in an unchanging state. Each engineer incrementally compiles local changes made to source files in his own user work space to produce a local set of compilation and processing results. Incremental compilation uses unedited source files, the basis from the global work space, and the user'"'"'s edited local files to produce the local processing results. Upon satisfactory results, edited source files and local processing results may replace and overwrite global files and results. Multiple engineers are allowed to work on complex logic design that can be implemented on a single, large capacity device.

Claims

1. A method of incrementally compiling an electronic design within a work group computing system for implementation on a target hardware device, said method comprising:

compiling a plurality of project source files representing said electronic design to produce a global basis specifying compilation results;

accepting a modification to said electronic design from a user associated with said work group computing system;

delineating a sphere of influence of said modification within said electronic design; and

recompiling that portion of said electronic design within said sphere of influence of said modification to produce a local basis specifying compilation results for said user, whereby said electronic design is recompiled in an efficient manner to incorporate said modification from said user.

2. A method as recited in claim 1 wherein said delineating further includes:

receiving an unsynthesized netlist for said electronic design, and an unsynthesized netlist representing said electronic design as modified by said user;

comparing said unsynthesized netlists using netlist differencing to identify a sub-netlist of said electronic design that defines a changed portion of said electronic design; and

synthesizing said sub-netlist, whereby said synthesized sub-netlist may be recompiled.

3. A method as recited in claim 1 wherein said recompiling further includes:

synthesizing that portion of said electronic design within said sphere of influence of said modification;

mapping said portion to said target hardware device; and

fitting said portion to said target hardware device, whereby said modification of said user in incorporated into said target hardware device.

4. A method as recited in claim 1 further comprising:

determining whether said portion of said electronic design modified by said user fits within said target hardware device.

5. A method as recited in claim 4 further comprising:

wherein when it is determined that said portion does not fit, relaxing constraints upon placement of said electronic design within said target hardware device in a predetermined manner until said portion does fit.

6. A method as recited in claim 1 wherein said target hardware device is a programmable logic device (PLD), an application specific integrated circuit (ASIC), a printed circuit board or a multi-chip module.

7. A method of incrementally compiling an electronic design for implementation on a target hardware device, said method comprising:

receiving a modification to an original electronic design from a user, said modification represented in a changed electronic design;

receiving an unsynthesized netlist for said original electronic design and an unsynthesized netlist for said changed electronic design;

performing netlist differencing of said unsynthesized netlists to identify a sub-netlist of said original electronic design that defines a changed portion of said original electronic design;

synthesizing said sub-netlist; and

recompiling said synthesized sub-netlist into said target hardware device, whereby said changed electronic design is recompiled in an efficient manner to incorporate said modification from said user.

8. A method as recited in claim 7 wherein said user is part of a workgroup and said method further comprises:

compiling a plurality of project source files representing said original electronic design, said source files originating from a plurality of users.

9. A method as recited in claim 7 wherein said recompiling further includes:

mapping said synthesized sub-netlist to said target hardware device; and

fitting said synthesized sub-netlist to said target hardware device, whereby said modification of said user in incorporated into said target hardware device.

10. A method as recited in claim 7 further comprising:

determining whether said changed electronic design fits within said target hardware device.

11. A method as recited in claim 10 further comprising:

wherein when it is determined that said changed electronic design does not fit, relaxing constraints upon placement of said changed electronic design within said target hardware device in a predetermined manner until said changed electronic design does fit.

12. A method as recited in claim 7 wherein said target hardware device is a programmable logic device (PLD), an application specific integrated circuit (ASIC), a printed circuit board or a multi-chip module.

13. A computer-readable medium comprising computer code for incrementally compiling an electronic design within a work group computing system for implementation on a target hardware device, said computer code of said computer-readable medium effecting the following:

compiling a plurality of project source files representing said electronic design to produce a global basis specifying compilation results;

accepting a modification to said electronic design from a user associated with said work group computing system;

delineating a sphere of influence of said modification within said electronic design; and

recompiling that portion of said electronic design within said sphere of influence of said modification to produce a local basis specifying compilation results for said user, whereby said electronic design is recompiled in an efficient manner to incorporate said modification from said user.

14. A computer-readable medium as recited in claim 13 wherein said delineating further includes computer code for:

receiving an unsynthesized netlist for said electronic design, and an unsynthesized netlist representing said electronic design as modified by said user;

comparing said unsynthesized netlists using netlist differencing to identify a sub-netlist of said electronic design that defines a changed portion of said electronic design; and

synthesizing said sub-netlist, whereby said synthesized sub-netlist may be recompiled.

15. A computer-readable medium as recited in claim 13 wherein said recompiling further includes computer code for:

synthesizing that portion of said electronic design within said sphere of influence of said modification;

mapping said portion to said target hardware device; and

fitting said portion to said target hardware device, whereby said modification of said user in incorporated into said target hardware device.

16. A computer-readable medium as recited in claim 13 further comprising computer code for:

determining whether said portion of said electronic design modified by said user fits within said target hardware device.

17. A computer-readable medium as recited in claim 16, where in when it is determined that said portion does not fit, further comprises computer code for:

relaxing constraints upon placement of said electronic design within said target hardware device in a predetermined manner until said portion does fit.

18. A computer-readable medium as recited in claim 13 wherein said target hardware device is a programmable logic device (PLD), an application specific integrated circuit (ASIC), a printed circuit board or a multi-chip module.

19. A computer-readable medium comprising computer code for incrementally compiling an electronic design for implementation on a target hardware device, said computer code of said computer-readable medium effecting the following:

receiving a modification to an original electronic design from a user, said modification represented in a changed electronic design;

receiving an unsynthesized netlist for said original electronic design and an unsynthesized netlist for said changed electronic design;

performing netlist differencing of said unsynthesized netlists to identify a sub-netlist of said original electronic design that defines a changed portion of said original electronic design;

synthesizing said sub-netlist; and

recompiling said synthesized sub-netlist into said target hardware device, whereby said changed electronic design is recompiled in an efficient manner to incorporate said modification from said user.

20. A computer-readable medium as recited in claim 19 wherein said user is part of a workgroup and said method further comprises computer code for:

compiling a plurality of project source files representing said original electronic design, said source files originating from a plurality of users.

21. A computer-readable medium as recited in claim 19 wherein said recompiling further includes computer code for:

mapping said synthesized sub-netlist to said target hardware device; and

fitting said synthesized sub-netlist to said target hardware device, whereby said modification of said user in incorporated into said target hardware device.

22. A computer-readable medium as recited in claim 19 further comprising computer code for:

determining whether said changed electronic design fits within said target hardware device.

23. A computer-readable medium as recited in claim 22 wherein when it is determined that said changed electronic design does not fit, further comprises computer code for:

relaxing constraints upon placement of said changed electronic design within said target hardware device in a predetermined manner until said changed electronic design does fit.

24. A computer-readable medium as recited in claim 19 wherein said target hardware device is a programmable logic device (PLD), an application specific integrated circuit (ASIC), a printed circuit board or a multi-chip module.