System and method for testing an embedded microprocessor system containing physical and/or simulated hardware
First Claim
1. A system for testing an embedded electronic systems having a target processor executing a target program and coupled to target hardware, the target hardware consisting of one of physical target hardware, simulated target hardware, and combinations thereof, the system comprising:
- a hardware simulator configured to simulate the simulated target hardware;
a target monitor coupled to the target processor, the target monitor being operative to determine when the target processor is attempting to communicate with the simulated target hardware and to suspend execution of the target program in response thereto, the target monitor further being operative to convert output signals from the target processor that are directed to the simulated target hardware to corresponding output data and to convert input data from the hardware simulator to corresponding input signals that are applied to the target processor; and
a communications interface coupling the target monitor to the hardware simulator, the communications interface being operative to transfer the output data from the target monitor to the hardware simulator and being operative to transfer the input data from the hardware simulator to the target monitor.
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Accused Products
Abstract
A system for testing an embedded system containing a target processor executing a target program and target hardware that may be partially physical and partially simulated. A target monitor determines when the target processor is attempting to access the simulated hardware. This determination is made by monitoring the address bus of the microprocessor to detect an address in the address space of the simulated hardware. An attempt to access the simulated hardware may also be detected by detecting the lack of an acknowledge signal from the physical hardware within a predetermined period after the target processor attempts to access the target hardware. In the event of an access to the simulated hardware, a bus capture circuit captures output signals on the bus connections of the target processor and converts the output signals to output data. The output data is then coupled through a communications interface to a hardware simulator. The hardware simulator processes the data in the same manner that the physical hardware would respond to signals corresponding to the output data. The hardware simulator may also generate data that are converted to corresponding input signals and applied to respective bus connections of the target processor by a bus driver circuit. During the time that output data is being processed by the hardware simulator, execution of the target program by the target processor is suspended, although the target processor may continue to service interrupts.
82 Citations
28 Claims
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1. A system for testing an embedded electronic systems having a target processor executing a target program and coupled to target hardware, the target hardware consisting of one of physical target hardware, simulated target hardware, and combinations thereof, the system comprising:
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a hardware simulator configured to simulate the simulated target hardware;
a target monitor coupled to the target processor, the target monitor being operative to determine when the target processor is attempting to communicate with the simulated target hardware and to suspend execution of the target program in response thereto, the target monitor further being operative to convert output signals from the target processor that are directed to the simulated target hardware to corresponding output data and to convert input data from the hardware simulator to corresponding input signals that are applied to the target processor; and
a communications interface coupling the target monitor to the hardware simulator, the communications interface being operative to transfer the output data from the target monitor to the hardware simulator and being operative to transfer the input data from the hardware simulator to the target monitor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
a mapping memory recording addresses of the address space of the simulated target hardware; and
an address comparator coupled to the mapping memory and an address bus of the target processor, the address comparator comparing an address on the address bus to addresses recorded in the mapping memory and suspending execution of the target program in response to a match between the address on the address bus and one of the addresses recorded in the mapping memory.
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4. The system of claim 1 wherein the target monitor comprises:
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a control signal monitor monitoring a terminal on the target processor that is adapted to receive a control signal from the physical target hardware in the event of an access to the physical target hardware by the target processor, the control signal monitor generating a detect signal in response to receiving the control signal; and
a timer coupled to the target processor and the control signal monitor, the timer initiating a timing period responsive to an access by the target processor to the target hardware and suspending execution of the target program after the timing period has been initiated unless the detect signal has been received within a predetermined period after initiating the timing period.
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5. The system of claim 4 wherein the control signal comprises an acknowledge signal adapted to be generated by the physical target hardware responsive to an access by the target processor to the physical target hardware.
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6. The system of claim 1 wherein the target monitor comprises:
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a control processor to control operation of the target monitor;
a target processor bus driver circuit operative to receive the input signals from the control processor and to apply the input signals to the target processor; and
a target processor bus capture circuit operative to apply the output signals from the target processor to the control processor.
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7. The system of claim 1 wherein the communication interface comprises Ethernet link coupling the target monitor to the hardware simulator.
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8. The system of claim 1 wherein the hardware simulator comprises a host computer programmed with a hardware simulation program that simulates the simulated target hardware.
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9. The system of claim 8 further comprising a microprocessor emulator containing the target processor and a memory device containing the target program, the microprocessor emulator being coupled to the host computer to serve as a user interface for the emulator.
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10. A system for testing an embedded electronic systems having a target processor adapted to execute a target program, the target processor being coupled to target hardware, the target hardware consisting of one of physical target hardware, simulated target hardware having an address space with corresponding addresses, and combinations thereof, the system comprising:
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a hardware simulator configured to simulate the simulated target hardware;
a mapping memory recording addresses of the address space of the simulated target hardware;
an address comparator coupled to the mapping memory and an address bus of the target processor, the address comparator comparing an address on the address bus to addresses recorded in the mapping memory and suspending execution of the target program in response to a match between the address on the address bus and one of the addresses recorded in the mapping memory;
a target processor bus capture circuit operative to store output signals from the target processor responsive to the address comparator detecting a match between the address on the address bus and one of the addresses recorded in the mapping memory;
a signal converter converting the output signals stored in the bus capture circuit to corresponding output data; and
a communications interface coupling the signal converter to the hardware simulator, the communications interface transferring the output data from the signal converter to the hardware simulator. - View Dependent Claims (11, 12, 13, 14, 15)
a second signal converter coupled to the hardware simulator, the second signal converter converting input data from the hardware simulator to corresponding input signals; and
a target processor bus driver circuit coupled to the second signal converter, the target processor bus driver circuit being operative to apply the input signals to the target processor.
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12. The system of claim 10 further comprising a microprocessor emulator containing the target processor and a memory device containing the target program.
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13. The system of claim 10 wherein the communications interface comprises an Ethernet link coupling the signal converter to the hardware simulator.
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14. The system of claim 10 wherein the hardware simulator comprises a host computer programmed with a hardware simulation program that simulates the simulated target hardware.
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15. The system of claim 14 further comprising a microprocessor emulator containing the target processor and a memory device containing the target program, the microprocessor emulator being coupled to the host computer to serve as a user interface for the emulator.
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16. A system for testing an embedded electronic systems having a target processor adapted to execute a target program, the target processor being coupled to target hardware, the target hardware consisting of one of physical target hardware, simulated target hardware, and combinations thereof, the system comprising:
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a hardware simulator configured to simulate the simulated target hardware;
a control signal monitor monitoring a terminal on the target processor that is adapted to receive a control signal from the physical target hardware in the event of an access to the physical target hardware by the target processor, the control signal monitor generating a detect signal in response to receiving the control signal;
a timer coupled to the target processor and the control signal monitor, the timer initiating a timing period responsive to a target hardware access by the target processor and suspending execution of the target program after the timing period has been initiated unless the detect signal has been received within a predetermined period after initiating the timing period;
a target processor bus capture circuit operative to store output signals from the target processor after the timing period has been initiated unless the detect signal has been received within a predetermined period after initiating the timing period;
a signal converter converting the output signals stored in the bus capture circuit to corresponding output data; and
a communications interface coupling the signal converter to the hardware simulator, the communications interface transferring the output data from the signal converter to the hardware simulator. - View Dependent Claims (17, 18, 19, 20, 21)
a second signal converter coupled to the hardware simulator, the second signal converter converting input data from the hardware simulator to corresponding input signals; and
a target processor bus driver circuit coupled to the second signal converter, the target processor bus driver circuit being operative to apply the input signals to the target processor.
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18. The system of claim 16 further comprising a microprocessor emulator containing the target processor and a memory device containing the target program.
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19. The system of claim 16 wherein the communications interface comprises an Ethernet link coupling the signal converter to the hardware simulator.
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20. The system of claim 16 wherein the hardware simulator comprises a host computer programmed with a hardware simulation program that simulates the simulated portion of the target hardware.
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21. The system of claim 20 further comprising a microprocessor emulator containing the target processor and a memory device containing the target program, the microprocessor emulator being coupled to the host computer to serve as a user interface for the emulator.
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22. A system for testing an embedded electronic systems having a target processor executing a target program and coupled to target hardware, the target hardware consisting of one of physical target hardware, simulated target hardware, and combinations thereof, the system comprising:
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a hardware simulator configured to simulate the simulated target hardware;
a target monitor coupled to the target processor, the target monitor comprising;
a control signal monitor monitoring a terminal on the target processor that is adapted to receive a control signal from the physical target hardware in the event of an access to the physical target hardware by the target processor, the control signal monitor generating a detect signal in response to receiving the control signal; and
a timer coupled to the target processor and the control signal monitor, the timer initiating a timing period responsive to an access by the target processor to the target hardware and suspending execution of the target program after the timing period has been initiated unless the detect signal has been received within a predetermined period after initiating the timing period, the target monitor further being operative to convert output signals from the target processor that are directed to the simulated target hardware to corresponding output data; and
a communications interface coupling the target monitor to the hardware simulator, the communications interface being operative to transfer the output data from the target monitor to the hardware simulator. - View Dependent Claims (23, 24, 25, 26, 27)
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28. A system for testing an embedded electronic systems having a target processor executing a target program and coupled to target hardware, the target hardware consisting of one of physical target hardware, simulated target hardware having an address space with corresponding addresses, and combinations thereof, the system comprising:
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a hardware simulator configured to simulate the simulated target hardware;
a target monitor coupled to the target processor, the target monitor comprising;
a mapping memory recording addresses of the address space of the simulated target hardware; and
an address comparator coupled to the mapping memory and an address bus of the target processor, the address comparator comparing an address on the address bus to addresses recorded in the mapping memory and suspending execution of the target program in response to a match between the address on the address bus and one of the addresses recorded in the mapping memory, the target monitor further being operative to convert output signals from the target processor that are directed to the simulated target hardware to corresponding output data; and
a communications interface coupling the target monitor to the hardware simulator, the communications interface being operative to transfer the output data from the target monitor to the hardware simulator.
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Specification