High performance load/store functional unit and data cache

• US 6,298,423 B1
• Filed: 08/26/1996
• Issued: 10/02/2001
• Est. Priority Date: 10/29/1993
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Chinnakonda, Murali, Johnson, William M., Witt, David B.
• Primary Examiner(s): Ellis, Kevin L.
• Application Number:
  US08/703,299
• Time in Patent Office: 1,863 Days
• Field of Search: 711/131, 711/140, 711/149, 711/154, 712/23
• US Class Current: 711/154
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3826 Bypassing or forwarding of data results, e.g. locally between pipeline stages or within a pipeline stage
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution

Abstract

A load/store functional unit and a corresponding data cache of a superscalar microprocessor is disclosed. The load/store functional unit includes a plurality of reservation station entries which are accessed in parallel and which are coupled to the data cache in parallel. The load/store functional unit also includes a store buffer circuit having a plurality of store buffer entries. The store buffer entries are organized to provide a first in first out buffer where the outputs from less significant entries of the buffer are provided as inputs to more significant entries of the buffer.

Claims

1. An apparatus for buffering store information and for providing store forwarding of the store information, the apparatus comprising:

a first store buffer entry coupled to receive first store information from a store information providing circuit; and

a second store buffer entry coupled to receive second store information from the store information providing circuit when a second store address does not match a first store address, the second store buffer entry being coupled to receive the second store information from at least one of the store information providing circuit and the first store buffer entry when the second store address matches the first store address;

wherein the store information providing circuit includes

a merge circuit coupled to receive a number N data bytes from a data cache and N data bytes from a reservation station circuit, the N data bytes from the reservation station circuit including at least one updated data byte, the merge circuit replacing at least one data byte of the N data bytes from the data cache with a corresponding at least one updated data byte from the reservation station circuit to provide N store data bytes including the at least one updated data byte to one of the first and second store buffer entries responsive to receiving the data bytes from the data cache and the reservation station circuit.

2. An apparatus as recited in claim 1 wherein

the first store buffer entry includes:

a first data register circuit, the first data register circuit storing first store data of the first store information; and

a first tag register circuit, the first tag register circuit storing first tag information of the first store information; and

the second store buffer entry includes;

a second data register circuit, the second data register circuit storing second store data of the second store information; and

a second tag register circuit, the second tag register circuit storing second tag information of the second store information; and

further comprising;

a tag control circuit coupled to receive tag information from the store information providing circuit, the tag control circuit causing the second data register circuit to receive at least a first portion of the second store data from the store information providing circuit, the tag control circuit causing the second data register circuit to receive at least a second portion of the second store data from the first store buffer entry when the second store address matches the first store address and the first tag information matches the tag information received by the tag control circuit from the store information providing circuit.

3. An apparatus as recited in claim 2 wherein:

the second store buffer entry includes a data multiplexer circuit;

the second store data includes a plurality of data bytes;

the second tag information includes a plurality of tags, each of the plurality of tags corresponding to a respective one of the plurality of data bytes of the second store data; and

the tag control circuit controls the data multiplexer circuit to select at least one data byte of the second store data from the store information providing circuit for which a corresponding tag matches tag information received by the tag control circuit from the store information providing circuit and to select at least another data byte of the second store data from the first store buffer entry.

4. An apparatus as recited in claim 1 wherein the store information providing circuit comprises:

a reservation station circuit coupled to the first and second store buffer entries.

5. An apparatus as recited in claim 1 wherein the store information providing circuit further comprises:

a result bus coupled to the first and second store buffer entries and to a functional unit of a microprocessor.

6. An apparatus as recited in claim 1 wherein the store information providing circuit comprises:

a result bus coupled to the first and second store buffer entries and to a functional unit of a microprocessor.

7. An apparatus as recited in claim 1 wherein

each of the first and second store information includes:

store data information;

store address information; and

store tag information;

the store address information of the first store information includes the first store address; and

the store address information of the second store information includes the second store address.

8. An apparatus as recited in claim 1 wherein the apparatus further comprises:

a third store buffer entry coupled to receive third store information from the store information providing circuit when a third store address does not match at least one of the first and second store addresses, the third store buffer entry being coupled to receive the third store information from at least one of the store information providing circuit and the first and second store buffer entries when the third store address matches at least one of the first and second store addresses.

9. An apparatus as recited in claim 8 wherein the apparatus further comprises:

a fourth store buffer entry coupled to receive fourth store information from the store information providing circuit when a fourth store address does not match at least one of the first, second and third store addresses, the fourth store buffer entry being coupled to receive the fourth store information from at least one of the store information providing circuit and the first, second and third store buffer entries when the fourth store address matches at least one of the first, second and third store addresses.

10. An apparatus as recited in claim 1 wherein each store entry comprises:

a plurality of data bytes; and

a valid indication for each of the plurality of data bytes, and wherein

the at least one updated data byte is indicated by setting a corresponding at least one valid indication for the at least one updated data byte.

11. An apparatus as recited in claim 1 wherein the first and second store addresses are linear addresses.

12. An apparatus as recited in claim 1 wherein:

the first store buffer entry is coupled to receive the first store information from the store information providing circuit when the first store buffer entry stores no valid information and the second store buffer entry stores no valid information; and

the first store buffer entry is coupled to receive the first store information from the second store buffer entry when the first store buffer entry stores no valid information and the second store buffer entry stores valid information.

13. An apparatus as recited in claim 1 wherein

the first store buffer entry includes:

a first data register circuit, the first data register circuit storing first store data of the first store information; and

a first address register circuit, the first address register circuit storing the first store address of the first store information; and

further comprising;

an address compare circuit coupled to receive store addresses from the store information providing circuit, the address compare circuit causing the first data register circuit to forward the first store data to a load circuit responsive to receiving the first store address from the store information providing circuit while the first store address is stored in the first address register circuit to perform a load forwarding operation.

14. An apparatus as recited in claim 13 wherein

the second store buffer entry includes:

a second data register circuit, the second data register circuit storing second store data of the second store information; and

a second address register circuit, the second address register circuit storing the second store address of the second store information; and

the address compare circuit causes the second data register circuit to forward the second store data to the load circuit responsive to receiving the second store address from the store information providing circuit while the second store address is stored in the second address register circuit to perform a load forwarding operation.

15. An apparatus as recited in claim 1 wherein said apparatus comprises an integrated circuit microprocessor chip, further comprising:

a plurality of functional units;

an instruction processing circuit coupled to the functional units; and

a cache memory coupled to the instruction processing circuit.

16. An apparatus as recited in claim 1 coupled into a computer system having a processor, a memory and a bus coupled there between, said apparatus including circuits of the processor.

17. An apparatus for buffering store information and for providing store forwarding of the store information, the apparatus comprising:

a first store buffer entry coupled to receive first store information from a store information providing circuit, the first store buffer entry including a first data register circuit, the first data register circuit storing first store data of the first store information and a first address register circuit, the first address register circuit storing the first store address of the first store information, the first store buffer entry including

a first data register circuit, the first data register circuit storing first store data of the first store information; and

a first tag register circuit, the first tag register circuit storing first tag information of the first store information;

a second store buffer entry coupled to receive second store information from the store information providing circuit when a second store address does not match a first store address, the second store buffer entry being coupled to receive the second store information from at least one of the store information providing circuit and the first store buffer entry when the second store address matches the first store address, the second store buffer entry including

a second data register circuit, the second data register circuit storing second store data of the second store information; and

a second tag register circuit, the second tag register circuit storing second tag information of the second store information;

an address compare circuit coupled to receive store addresses from the store information providing circuit, the address compare circuit causing the first data register circuit to forward the first store data to a load circuit responsive to receiving the first store address from the store information providing circuit while the first store address is stored in the first address register circuit to perform a load forwarding operation; and

,

a tag control circuit coupled to receive tag information from the store information providing circuit, the tag control circuit causing the second data register circuit to receive at least a first portion of the second store data from the store information providing circuit, the tag control circuit causing the second data register circuit to receive at least a second portion of the second store data from the first store buffer entry when the second store address matches the first store address and the first tag information matches the tag information received by the tag control circuit from the store information providing circuit,

wherein

the second store buffer entry includes a data multiplexer circuit;

the second store data includes a plurality of data bytes;

the second tag information includes a plurality of tags, each of the plurality of tags corresponding to a respective one of the plurality of data bytes of the second store data; and

the tag control circuit controls the data multiplexer circuit to select at least one data byte of the second store data from the store information providing circuit for which a corresponding tag matches tag information received by the tag control circuit from the store information providing circuit and to select at least another data byte of the second store data from the first store buffer entry.

18. An apparatus for buffering store information and for providing store forwarding of the store information, the apparatus comprising:

a first store buffer entry coupled to receive first store information from a store information providing circuit, the first store buffer entry including a first data register circuit, the first data register circuit storing first store data of the first store information and a first address register circuit, the first address register circuit storing the first store address of the first store information, the first store buffer entry including

a first data register circuit, the first data register circuit storing first store data of the first store information; and

a first address register circuit, the first address register circuit storing the first store address of the first store information; and

a second store buffer entry coupled to receive second store information from the store information providing circuit when a second store address does not match a first store address, the second store buffer entry being coupled to receive the second store information from at least one of the store information providing circuit and the first store buffer entry when the second store address matches the first store address; and

,

an address compare circuit coupled to receive store addresses from the store information providing circuit, the address compare circuit causing the first data register circuit to forward the first store data to a load circuit responsive to receiving the first store address from the store information providing circuit while the first store address is stored in the first address register circuit to perform a load forwarding operation.

19. An apparatus as recited in claim 18 wherein the store information providing circuit comprises:

a reservation station circuit coupled to the first and second store buffer entries.

20. An apparatus as recited in claim 19 wherein the store information providing circuit further comprises:

a result bus coupled to the first and second store buffer entries and to a functional unit of a microprocessor.

21. An apparatus as recited in claim 18 wherein the store information providing circuit comprises:

a result bus coupled to the first and second store buffer entries and to a functional unit of a microprocessor.

22. An apparatus as recited in claim 18 wherein

each of the first and second store information includes:

store data information;

store address information; and

store tag information;

the store address information of the first store information includes the first store address;

and

the store address information of the second store information includes the second store address.

23. An apparatus as recited in claim 18 wherein the apparatus further comprises:

a third store buffer entry coupled to receive third store information from the store information providing circuit when a third store address does not match at least one of the first and second store addresses, the third store buffer entry being coupled to receive the third store information from at least one of the store information providing circuit and the first and second store buffer entries when the third store address matches at least one of the first and second store addresses.

24. An apparatus as recited in claim 23 wherein the apparatus further comprises:

a fourth store buffer entry coupled to receive fourth store information from the store information providing circuit when a fourth store address does not match at least one of the first, second and third store addresses, the fourth store buffer entry being coupled to receive the fourth store information from at least one of the store information providing circuit and the first, second and third store buffer entries when the fourth store address matches at least one of the first, second and third store addresses.

25. An apparatus as recited in claim 18 wherein the first and second store addresses are linear addresses.

26. An apparatus as recited in claim 18 wherein

the first store buffer entry is coupled to receive the first store information from the store information providing circuit when the first store buffer entry stores no valid information and the second store buffer entry stores no valid information;

and

the first store buffer entry is coupled to receive the first store information from the second store buffer entry when the first store buffer entry stores no valid information and the second store buffer entry stores valid information.

27. An apparatus as recited in claim 18 wherein

the second store buffer entry includes

a second data register circuit, the second data register circuit storing second store data of the second store information;

and

a second address register circuit, the second address register circuit storing the second store address of the second store information; and

the address compare circuit causes the second data register circuit to forward the second store data to the load circuit responsive to receiving the second store address from the store information providing circuit while the second store address is stored in the second address register circuit to perform a load forwarding operation.

28. An apparatus as recited in claim 18 wherein said apparatus comprises an integrated circuit microprocessor chip further comprising:

a plurality of functional units;

an instruction processing circuit coupled to the functional units; and

a cache memory coupled to the instruction processing circuit.

29. An apparatus as recited in claim 18 coupled into a computer system having a processor, a memory and a bus coupled therebetween, said apparatus including circuits of the processor.

30. An apparatus for buffering store information and for providing store forwarding of the store information, the apparatus comprising:

a first store buffer entry coupled to receive first store information from a store information providing circuit, the first store buffer entry including a first data register circuit, the first data register circuit storing first store data of the first store information and a first address register circuit, the first address register circuit storing the first store address of the first store information;

a second store buffer entry coupled to receive second store information from the store information providing circuit when a second store address does not match a first store address, the second store buffer entry being coupled to receive the second store information from at least one of the store information providing circuit and the first store buffer entry when the second store address matches the first store address; and

,

an address compare circuit coupled to receive store addresses from the store information providing circuit, the address compare circuit causing the first data register circuit to forward the first store data to a load circuit responsive to receiving the first store address from the store information providing circuit while the first store address is stored in the first address register circuit to perform a load forwarding operation

wherein the store information providing circuit comprises;

a merge circuit coupled to receive a number N data bytes from a data cache and N data bytes from a reservation station circuit, the N data bytes from the reservation station circuit including at least one updated data byte, the merge circuit replacing at least one data byte of the N data bytes from the data cache with a corresponding at least one updated data byte from the reservation station circuit to provide N store data bytes including the at least one updated data byte to one of the first and second store buffer entries responsive to receiving the data bytes from the data cache and the reservation station circuit.

31. An apparatus as recited in claim 30 wherein each store entry comprises:

a plurality of data bytes; and

a valid indication for each of the plurality of data bytes, and wherein

the at least one updated data byte is indicated by setting a corresponding at least one valid indication for the at least one updated data byte.