Computer system including priorities for memory operations and allowing a higher priority memory operation to interrupt a lower priority memory operation

• US 6,298,424 B1
• Filed: 03/10/2000
• Issued: 10/02/2001
• Est. Priority Date: 12/02/1997
• Status: Expired due to Term

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Lewchuk, W. Kurt, McMinn, Brian D., Pickett, James K.
• Primary Examiner(s): Yoo, Do Hyun
• Assistant Examiner(s): Encarnacion, Yamir
• Application Number:
  US09/522,649
• Time in Patent Office: 571 Days
• Field of Search: 711/151, 711/158, 711/137, 709/240, 710/113, 710/114, 710/119-121, 710/40, 710/240-244, 710/264, 710/48, 712/207
• US Class Current: 711/158
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

A computer system includes one or more microprocessors. The microprocessors assign a priority level to each memory operation as the memory operations are initiated. In one embodiment, the priority levels employed by the microprocessors include a fetch priority level and a prefetch priority level. The fetch priority level is higher priority than the prefetch priority level, and is assigned to memory operations which are the direct result of executing an instruction. The prefetch priority level is assigned to memory operations which are generated according to a prefetch algorithm implemented by the microprocessor. As memory operations are routed through the computer system to main memory and corresponding data transmitted, the elements involved in performing the memory operations are configured to interrupt the transfer of data for the lower priority memory operation in order to perform the data transfer for the higher priority memory operation. While one embodiment of the computer system employs at least a fetch priority and a prefetch priority, the concept of applying priority levels to various memory operations and interrupting data transfers of lower priority memory operations to higher priority memory operations may be extended to other types of memory operations, even if prefetching is not employed within a computer system. For example, speculative memory operations may be prioritized lower than non-speculative memory operations throughout the computer system.

Claims

1. A computer system comprising:

one or more microprocessors, wherein said one or more microprocessors are configured to initiate a first memory operation and to subsequently initiate a second memory operation, and wherein said one or more microprocessors are configured to assign a first priority to said first memory operation, and wherein said one or more microprocessors are configured to assign a second priority to said second memory operation;

a main memory configured to store data including a first data corresponding to said first memory operation and a second data corresponding to said second memory operation; and

a bus bridge coupled to said one or more microprocessors and to said main memory, wherein said one or more microprocessors are configured to convey said first memory operation and to concurrently convey said first priority to said bus bridge, and wherein said one or more microprocessors are further configured to convey said second memory operation and to concurrently convey said second priority to said bus bridge, and wherein said bus bridge is configured to initiate a transfer of said first data responsive to said first memory operation, and wherein said bus bridge is configured to interrupt said transfer of said first data in response to said second memory operation if said second priority is higher than said first priority, and wherein said bus bridge is configured to inhibit interruption of transferring said first data if said first memory operation and said second memory operation are in different pages of said main memory.

2. The computer system as recited in claim 1 wherein said first memory operation is a read and said second memory operation is a write, and wherein said second priority is higher than said first priority.

3. The computer system as recited in claim 1 wherein said one or more microprocessors are configured to assign each of said first priority and said second priority to one of at least two priority levels.

4. The computer system as recited in claim 3 wherein said at least two priority levels include a prefetch priority level and a fetch priority level.

5. The computer system as recited in claim 4 wherein said fetch priority level is higher than said prefetch priority level.

6. The computer system as recited in claim 3 wherein said at least two priority levels include a non-speculative priority level and a speculative priority level.

7. The computer system as recited in claim 6 wherein said non-speculative priority level is higher than said speculative priority level.

8. The computer system as recited in claim 3 wherein said at least two priority levels includes a fill priority level and a write back priority level.

9. The computer system as recited in claim 8 wherein said fill priority level is higher than said write back priority level.

10. The computer system as recited in claim 1 wherein said first memory operation is initiated by a first microprocessor of said one or more microprocessors and wherein said second memory operation is initiated by a second microprocessor of said one or more microprocessors.

11. The computer system as recited in claim 1 wherein said first memory operation and said second memory operation are initiated by a same one of said one or more microprocessors.

12. The computer system as recited in claim 1 wherein said bus bridge is configured to transfer said second data while transfer of said first data is interrupted.

13. The computer system as recited in claim 12 wherein said bus bridge is configured to resume transferring said first data upon completing transfer of said second data.

14. The computer system as recited in claim 1 wherein said bus bridge is configured to interrupt a transfer of said first data between said main memory and said bus bridge.

15. The computer system as recited in claim 1 wherein said first data comprises a plurality of beats of data, each of said plurality of beats of data transferred at a different time, and wherein interrupting said transfer is performed between two beats of the plurality of beats.

16. A method for transferring data in a computer system, comprising:

receiving a first memory operation and concurrently receiving a first priority of said first memory operation, said first priority assigned by a microprocessor initiating said first memory operation;

receiving a second memory operation and concurrently receiving a second priority of said second memory operation, said second priority assigned by a microprocessor initiating said second memory operation, said receiving and said concurrently receiving being subsequent to said receiving said first memory operation;

transferring data corresponding to said first memory operation; and

interrupting said transferring if said second priority is higher than said first priority, and transferring data corresponding to said second memory operation during said interrupting, wherein said interrupting is inhibited if a first memory address corresponding to said first memory operation is in a different page than a second memory address corresponding to said second memory operation.

17. The method as recited in claim 16 wherein said first memory operation is a read and said second memory operation is a write, and wherein said second priority is higher than said first priority.

18. The method as recited in claim 16 further comprising transferring a remaining portion of said data corresponding to said first memory operation subsequent to said interrupting.

19. The method as recited in claim 16 wherein said data corresponding to said first memory operation comprises a plurality of beats of data, each of said plurality of beats of data transferred at a different time, and wherein said interrupting is performed between two beats of the plurality of beats.

20. A bus bridge for a computer system, comprising:

a CPU interface block coupled to receive memory operations, said CPU interface block further coupled to receive a corresponding priority for each memory operation, said priority assigned by one or more microprocessors initiating said memory operation; and

a memory controller coupled to said CPU interface block and a memory, wherein said memory controller is configured to receive said each memory operation and said corresponding priority from said CPU interface block, and wherein said memory controller is configured to interrupt an in-progress memory operation to service a subsequent memory operation if a first priority corresponding to said in-progress memory operation is lower than a second priority corresponding to said subsequent memory operation, and wherein said memory controller is configured to inhibit interrupt of said in-progress memory operation if said in-progress memory operation is to a different page of said memory than said subsequent memory operation.

21. The bus bridge as recited in claim 20 wherein said memory controller is configured to resume said in-progress memory operation after servicing said subsequent memory operation.

22. The bus bridge as recited in claim 20 wherein said in-progress memory operation is a read and said subsequent memory operation is a write, and wherein said second priority is higher than said first priority.

23. The bus bridge as recited in claim 20 wherein interrupting said in-progress memory operation is performed between a transfer of a first beat of a plurality of beats of data accessed in response to said in-progress memory operation and a transfer of a second beat of a plurality of beats of data accessed in response to said in-progress memory operation.

24. A bus bridge for a computer system, comprising:

a CPU interface block coupled to receive memory operations; and

a memory controller coupled to said CPU interface block and a memory, wherein said memory controller is configured to receive a first memory operation from said CPU interface block, and wherein said memory controller is configured to interrupt an in-progress memory operation to service said first memory operation if said first memory operation is higher priority than said in-progress memory operation, and wherein the memory controller is configured to inhibit interrupt of said in-progress memory operation if said in-progress memory operation is to a different page of said memory than said first memory operation.

25. The bus bridge as recited in claim 24 wherein said CPU interface block is further coupled to receive a corresponding priority for each memory operation, said priority assigned by one or more microprocessors initiating said memory operation.

26. The bus bridge as recited in claim 24 wherein said memory controller is configured to resume said in-progress memory operation after servicing said subsequent memory operation.

27. The bus bridge as recited in claim 24 wherein said in-progress memory operation is a read and said first memory operation is a write.

28. The bus bridge as recited in claim 24 wherein said in-progress memory operation is a prefetch and said first memory operation is a fetch.

29. The bus bridge as recited in claim 24 wherein said in-progress memory operation is speculative and said first memory operation is non-speculative.

30. The bus bridge as recited in claim 24 wherein said in-progress memory operation is a writeback and said first memory operation is a fill.

31. The bus bridge as recited in claim 24 wherein said memory controller is configured to transfer data corresponding to said first memory operation while said in-progress memory operation is interrupted.

32. A method for transferring data in a computer system, comprising:

receiving a first memory operation;

receiving a second memory operation subsequent to said receiving said first memory operation;

transferring data corresponding to said first memory operation; and

interrupting said transferring if said second memory operation is higher priority than said first memory operation, and transferring data corresponding to said second memory operation during said interrupting, and wherein said interrupting is inhibited if a first memory address corresponding to said first memory operation is in a different page than a second memory address corresponding to said second memory operation.

33. The method as recited in claim 32 wherein said first memory operation is a read and said second memory operation is a write.

34. The method as recited in claim 32 further comprising transferring a remaining portion of said data corresponding to said first memory operation subsequent to said interrupting.

35. The method as recited in claim 32 further comprising

assigning a first priority to said first memory operation by a microprocessor initiating said first memory operation and conveying said first priority;

receiving the first priority concurrent with said receiving said first memory operation;

assigning a second priority to said second memory operation by a microprocessor initiating said second memory operation and conveying said second priority; and

receiving the second priority concurrent with said receiving said second memory operation.