Banked shadowed register file

• US 6,298,431 B1
• Filed: 12/31/1997
• Issued: 10/02/2001
• Est. Priority Date: 12/31/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Gottlieb, Robert Steven
• Primary Examiner(s): BANANKHAH, MAJID A
• Application Number:
  US09/001,412
• Time in Patent Office: 1,371 Days
• Field of Search: 712/228, 712/15, 712/4, 712/5, 712/32, 712/33, 712/108, 709/100, 709/108, 709/102, 711/145, 711/131, 711/151
• US Class Current: 712/28
• CPC Class Codes: G06F 9/30116 Shadow registers, e.g. coupled registers, not forming part of the register space
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/462 with multiple register sets

Abstract

An apparatus and method for improving processor performance during multithreaded processing based on the use of a banked shadowed register file for minimizing thread switch overhead.

Claims

1. An apparatus, comprising:

a standard register of a register file coupled to an execution core over a first connection;

a plurality of shadowed registers to save program thread information;

an input transmission gate circuit coupled between the standard register and the plurality of shadowed registers over a second connection different than the first connection to transfer first data from the standard register to a first selected one of the plurality of shadowed registers; and

an output transmission gate circuit coupled between the plurality of shadowed registers and the standard register over a third connection different than the first connection to transfer second data from a second selected one of the plurality of shadowed registers to the standard register.

2. The apparatus of claim 1, further comprising:

a first temporary register coupled between the standard register and the input transmission gate circuit to temporarily store the first data; and

a second temporary register coupled between the output transmissiom gate circuit and the standard register to temporarily store the second data.

3. The apparatus of claim 1, further comprising a controller to select the first selected one and second selected one of the plurality of shadowed registers.

4. The apparatus of claim 1, wherein the first selected one of the plurality of shadowed registers and the second selected one of the plurality of shadowed registers are a same register.

5. The apparatus of claim 1, wherein the first selected one of the plurality of shadowed registers and the second selected one of the plurality of shadowed registers are different registers.

6. The apparatus of claim 1, wherein the input transmission gate and output transmission gate have mutually exclusive operation.

7. A method, comprising:

providing a standard register coupled to an execution core over a first connection;

providing a plurality of supplemental registers coupled to the standard register over a second connection different than the first connection; and

performing a program thread switch in the execution core by;

transferring a first data from the standard register to a first selected one of the plurality of supplemental registers over the second connection; and

transferring a second data from a second selected one of the plurality of supplemental registers to the standard register over the second connection.

8. The method of claim 7, wherein the first selected one and second selected one of the plurality of supplemental registers are selected by a control circuit.

9. The method of claim 7, wherein:

transferring the first data includes temporarily storing the first data in a first temporary register; and

transferring the second data includes temporarily storing the second data in a second temporary register.

10. The method of claim 7, wherein:

transferring the first data includes;

transferring the first data from the standard register to a first temporary register; and

subsequently transferring the first data from the first temporary register to the first selected one of the plurality of shadowed registers;

transferring the second data includes;

transferring the second data from the second selected one of the plurality of shadowed registers to a second temporary register; and

subsequently transferring the second data from the second temporary register to the standard register.

11. The method of claim 10, wherein transferring the first data to the first temporary register and transferring the second data from the second temporary register do not take place at the same time.

12. The method of claim 10, wherein:

transferring the first data from the first temporary register includes passing the first data through a first transmission gate; and

transferring the second data from the second selected one of the plurality of shadowed registers includes passing the second data through a second transmission gate.

13. A machine-readable medium having stored thereon instructions, which when executed by at least one processor cause said at least one processor to perform a thread switch in an execution core by:

transferring a first thread-based state data from a standard register coupled to an execution core to a first selected one of a plurality of supplemental registers over a first connection not coupled to the execution core; and

transferring a second thread-based state data from a second selected one of the plurality of supplemental registers to the standard register over a second connection not coupled to the execution core.

14. The medium of claim 13, wherein the first selected one and second selected one of the plurality of supplemental registers are selected by a control circuit.

15. The medium of claim 13, wherein:

transferring the first data includes temporarily storing the first data in a first temporary register; and

transferring the second data includes temporarily storing the second data in a second temporary register.

16. The medium of claim 13, wherein:

transferring the first data includes;

transferring the first data from the standard register to a first temporary register; and

subsequently transferring the first data from the first temporary register to the first selected one of the plurality of shadowed registers;

transferring the second data includes;

transferring the second data from the second selected one of the plurality of shadowed registers to a second temporary register; and

subsequently transferring the second data from the second temporary register to the standard register.

17. The medium of claim 16, wherein transferring the first data to the first temporary register and transferring the second data from the second temporary register do not take place at the same time.

18. The medium of claim 16, wherein:

transferring the first data from the first temporary register includes passing the first data through a first transmission gate; and

transferring the second data from the second selected one of the plurality of shadowed registers includes passing the second data through a second transmission gate.

19. A computer system, comprising:

a processor having an execution core;

a memory coupled to the processor;

a standard register of a register file coupled to the execution core over a first connection;

a plurality of shadowed registers to save program thread information;

an input transmission gate circuit coupled between the standard register and the plurality of shadowed registers over a second connection different than the first connection to transfer first data from the standard register to a first selected one of the plurality of shadowed registers; and

an output transmission gate circuit coupled between the plurality of shadowed registers and the standard register over a third connection different than the first connection to transfer second data from a second selected one of the plurality of shadowed registers to the standard register.

20. The system of claim 19, further comprising:

a first temporary register coupled between the standard register and the input transmission gate circuit to temporarily store the first data; and

a second temporary register coupled between the output transmission gate circuit and the standard register to temporarily store the second data.

21. The system of claim 19, further comprising a controller to select the first selected one and second selected one of the plurality of shadowed registers.

22. The system of claim 19, wherein the first selected one of the plurality of shadowed registers and the second selected one of the plurality of shadowed registers are a same register.

23. The system of claim 19, wherein the first selected one of the plurality of shadowed registers and the second selected one of the plurality of shadowed registers are different registers.

24. The system of claim 19, wherein the input transmission gate and output transmission gate have mutually exclusive operation.