Field effect transistor having dual gates with asymmetrical doping for reduced threshold voltage

• US 6,300,182 B1
• Filed: 12/11/2000
• Issued: 10/09/2001
• Est. Priority Date: 12/11/2000
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Yu, Bin
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): HOANG, QUOC DINH
• Application Number:
  US09/734,449
• Time in Patent Office: 302 Days
• Field of Search: 438/217, 438/231, 438/232, 438/276, 438/286, 438/289, 438/311, 438/373, 438/542
• US Class Current: 438/217
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78654 Monocrystalline silicon transistors

Abstract

For fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, a pillar of semiconductor material is formed on a layer of buried insulating material. The pillar has a top surface, a left side surface, a right side surface, a front side surface, and a back side surface, and the pillar has a width and a length. A dielectric structure comprised of a hardmask dielectric material is formed on the top surface of the pillar. A first gate dielectric is formed on the left side surface of the pillar, and a second gate dielectric is formed on the right side surface of the pillar, along a gate length of the length of the pillar. A gate electrode material is deposited on the dielectric structure and on the first gate dielectric and the second gate dielectric to surround the pillar at the top surface and the left and right side surfaces of the pillar for the gate length of the pillar. A first gate dopant is implanted at an angle directed toward the gate electrode material on the left side surface of the pillar such that the first gate dopant is not implanted into the gate electrode material on the right side surface of the pillar. In addition, a second gate dopant is implanted at an angle directed toward the gate electrode material on the right side surface of the pillar such that the second gate dopant is not implanted into the gate electrode material on the left side surface of the pillar. The first gate dopant is different from the second gate dopant such that a threshold voltage at the gate electrode material of the field effect transistor is less than about 0.4 Volts. The present invention may be used to particular advantage when the first gate dopant is an N-type dopant, and when the second gate dopant is a P-type dopant.

Claims

1. A method for fabricating a field effect transistor on a semiconductor substrate in SOI (semiconductor on insulator) technology, the method including the steps of:

A. forming a pillar of semiconductor material on a layer of buried insulating material, wherein said pillar has a top surface, a left side surface, a right side surface, a front side surface, and a back side surface, and wherein said pillar has a width and a length;

B. forming a dielectric structure comprised of a hardmask dielectric material on said top surface of said pillar;

C. forming a first gate dielectric on said left side surface of said pillar and forming a second gate dielectric on said right side surface of said pillar, along a gate length of said length of said pillar;

D. depositing a gate electrode material on said dielectric structure and on said first gate dielectric and said second gate dielectric to surround said pillar at said top surface and said left and right side surfaces of said pillar for said gate length of said pillar;

E. implanting a first gate dopant at an angle directed toward said gate electrode material on said left side surface of said pillar such that said first gate dopant is not implanted into said gate electrode material on said right side surface of said pillar; and

F. implanting a second gate dopant at an angle directed toward said gate electrode material on said right side surface of said pillar such that said second gate dopant is not implanted into said gate electrode material on said left side surface of said pillar;

wherein said first gate dopant is different from said second gate dopant such that a threshold voltage at said gate electrode material of said field effect transistor is less than about 0.4 Volts.

2. The method of claim 1, wherein said first gate dopant is an N-type dopant, and wherein said second gate dopant is a P-type dopant.

3. The method of claim 2, wherein said gate electrode material is comprised of one of polysilicon or polysilicon germanium.

4. The method of claim 3, wherein said first gate dopant is one of phosphorous or arsenic, and wherein said second gate dopant is boron.

5. The method of claim 1, wherein said first gate dopant and said second gate dopant are implanted at an angle in a range of from about 30 degrees to about 60 degrees with respect to a vertical line perpendicular to said semiconductor substrate.

6. The method of claim 1, wherein said pillar is comprised of silicon, and wherein said first gate dielectric and said second gate dielectric are comprised of silicon dioxide having a thickness in a range of from about 15 Å

(angstroms) to about 25 Å

(angstroms).

7. The method of claim 6, wherein said dielectric structure on said top surface of said pillar is comprised of silicon nitride.

8. The method of claim 1, further comprising the step of:

implanting a drain and source dopant into exposed regions of said pillar to form a drain of said field effect transistor on a first side of said gate electrode material along said length of said pillar toward said front side surface of said pillar and to form a source of said field effect transistor on a second side of said gate electrode material along said length of said pillar toward said back side surface of said pillar.

9. The method of claim 8, wherein said drain and source dopant is an N-type dopant for fabrication of an NMOSFET (N-channel Metal Oxide Semiconductor Field Effect Transistor).

10. The method of claim 8, wherein said drain and source dopant is a P-type dopant for fabrication of a PMOSFET (P-channel Metal Oxide Semiconductor Field Effect Transistor).

11. The method of claim 1, wherein said step A includes the steps of:

depositing said layer of buried insulating material on said semiconductor substrate;

depositing a layer of said semiconductor material of said pillar on said layer of buried insulating material;

depositing a layer of said hardmask dielectric material on said layer of semiconductor material;

patterning and etching a layer of photoresist material to mask said layer of hardmask dielectric material and said layer of semiconductor material of said pillar for said width and said length of said pillar; and

etching any region of said layer of hardmask dielectric material and said layer of semiconductor material not masked by said photoresist material to form said pillar of said semiconductor material with said hardmask dielectric material remaining to form said dielectric structure on said top surface of said pillar.

12. The method of claim 11, wherein said layer of said semiconductor material of said pillar has a thickness in a range of from about 300 Å

(angstroms) to about 600 Å

(angstroms).

13. The method of claim 1, wherein said width of said pillar is in a range of from about 100 Å

(angstroms) to about 250 Å

(angstroms).