Fabrication process for reduced area storage node junction

• US 6,300,188 B1
• Filed: 06/16/1999
• Issued: 10/09/2001
• Est. Priority Date: 11/16/1995
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gonzalez, Fernando
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US09/334,583
• Time in Patent Office: 846 Days
• Field of Search: 438/253-256, 438/393-399, 438/243-246, 438/386-392, 438/286, 438/238-239
• US Class Current: 438/239
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor

Abstract

An improved storage node junction between a doped active area in a semiconductor substrate and an overlying layer of polysilicon, such as the storage node junction in a DRAM memory cell. The area and perimeter of the storage node junction is significantly reduced and the junction is moved away from the adjacent isolation structure. An exemplary semiconductor device incorporating the new junction includes a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to LOCOS steps to create active areas bounded by a region of field oxide. An insulated gate electrode is formed over an active area on the substrate, which has been doped to a first conductivity type. A contact region comprising a portion of the active area extends laterally between one side of the gate electrode and the field oxide region. The contact region has a first segment adjacent to the gate electrode and a second segment interposed between the first segment and the field oxide region. The first segment is thereby isolated from the field oxide region by the second segment. The first segment is doped to a second conductivity type. A layer of storage polysilicon is formed in electrical contact with the first segment of the contact region but not the second segment of the contact region. The storage polysilicon is isolated from the field oxide through an insulating layer interposed between the storage polysilicon and the second segment of the contact region.

Claims

1. A process for fabricating a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to field isolation steps to create active areas bounded by a region of field oxide, the process comprising the steps of:

forming an insulated gate electrode over an active area on a first conductivity type substrate;

defining a contact region in the active area extending laterally between one side of the gate electrode and the field oxide region;

a first segment of the contact region adjacent to the gate electrode;

interposing a second segment of the contact region between the first segment and the field oxide region to completely physically and electrically isolate the first segment from the field oxide region;

then

forming a layer of insulating material over the entire contact region;

patterning and etching the layer of insulating material to expose at least a portion of only the first segment of the contact region;

then

implanting a second conductivity type dopant into only the exposed portion of first segment of the contact region;

then

forming a layer of polysilicon extending between the gate electrode and the field oxide region, the polysilicon layer having a generally horizontal portion over both segments of the contact region and the generally horizontal portion of the polysilicon layer in electrical contact with the exposed first segment of the contact region and electrically isolated from the second segment of the contact region by at least one layer of insulating material.

2. A process according to claim 1, wherein the insulating material is silicon nitride.

3. A process according to claim 1, further comprising the step of doping the layer of polysilicon to a second conductivity type.

4. A process according to claim 1, further comprising the step of heat treating the layer of polysilicon to out-diffuse the second conductivity type dopant therein into the first segment of the contact region.

5. A process for fabricating a dynamic random access memory cell, comprising the steps of:

providing an electrically insulated transistor gate electrode over a first conductivity type semiconductor substrate;

defining a first contact region for electrical connection to a bit line, the first contact region being defined in the substrate laterally adjacent to one side of the gate electrode;

defining a second contact region for electrical connection to a memory cell capacitor, the second contact region being defined in the substrate laterally adjacent to another side of the gate electrode and extending between the gate electrode and a region of field oxide;

defining a first segment of the second contact region adjacent to the gate electrode;

interposing a second segment of the second contact region between the first segment and the field oxide region to completely physically and electrically isolate the first segment from the field oxide region;

then

forming a layer of insulating material over the entire second contact region;

patterning and etching the layer of insulating material to expose at least a portion of only the first segment of the second contact region;

then

implanting a second conductivity type dopant into the first contact region and into only the exposed portion of first segment of the second contact region;

then

depositing a layer of storage polysilicon over the substrate, the storage polysilicon having a generally horizontal portion over both segments of the contact region and the generally horizontal portion of the storage polysilicon in contact with the exposed first segment of the second contact region and isolated from the second segment of the contact region by at least one layer of insulating material;

patterning and etching the layer of storage polysilicon to define a capacitor storage node;

depositing a dielectric layer over the capacitor storage node;

depositing a second layer of polysilicon over the dielectric layer; and

patterning and etching the second layer of polysilicon to define a capacitor cell plate.

6. A process according to claim 5, further comprising the step of doping the layer of polysilicon to a second conductivity type.

7. A process according to claim 5, further comprising the steps of:

forming an upper insulating layer over the cell plate and exposed upper surfaces of the other structures previously formed;

patterning and etching the upper insulating layer and continuing to etch down to expose portions of the first contact region; and

forming a bit line contact in electrical contact with the exposed portions of the first contact region.

8. A process according to claim 5, wherein the insulating material is silicon nitride.

9. A process according to claim 6, further comprising the step of heat treating the layer of polysilicon to out-diffuse the second conductivity type dopant therein into the first segment of the contact region.