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Fabrication process for reduced area storage node junction

  • US 6,300,188 B1
  • Filed: 06/16/1999
  • Issued: 10/09/2001
  • Est. Priority Date: 11/16/1995
  • Status: Expired due to Fees
First Claim
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1. A process for fabricating a storage node junction between a conductive polysilicon layer and an active area on a semiconductor substrate, the substrate having been subjected to field isolation steps to create active areas bounded by a region of field oxide, the process comprising the steps of:

  • forming an insulated gate electrode over an active area on a first conductivity type substrate;

    defining a contact region in the active area extending laterally between one side of the gate electrode and the field oxide region;

    a first segment of the contact region adjacent to the gate electrode;

    interposing a second segment of the contact region between the first segment and the field oxide region to completely physically and electrically isolate the first segment from the field oxide region;

    then forming a layer of insulating material over the entire contact region;

    patterning and etching the layer of insulating material to expose at least a portion of only the first segment of the contact region;

    then implanting a second conductivity type dopant into only the exposed portion of first segment of the contact region;

    then forming a layer of polysilicon extending between the gate electrode and the field oxide region, the polysilicon layer having a generally horizontal portion over both segments of the contact region and the generally horizontal portion of the polysilicon layer in electrical contact with the exposed first segment of the contact region and electrically isolated from the second segment of the contact region by at least one layer of insulating material.

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