Photodiode array with expanded dynamic range

• US 6,300,613 B1
• Filed: 05/20/1999
• Issued: 10/09/2001
• Est. Priority Date: 06/26/1998
• Status: Expired due to Fees

• Current Assignee: Hewlett-Packard Company (HP Inc.)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Kuderer, Hubert
• Primary Examiner(s): Le, Que T.
• Assistant Examiner(s): Luu, Thanh X.
• Application Number:
  US09/315,571
• Time in Patent Office: 873 Days
• Field of Search: 250/208.2, 250/208.1, 250/214.C, 250/214.R, 250/214.DC, 250/214.LA, 356/328, 356/326, 356/221-223
• US Class Current: 250/208.2
• CPC Class Codes: G01J 1/46 using a capacitor
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters

Abstract

A charge balance type of photodiode array uses parallel A/D conversion in each channel of the photodiode array. The charge caused by the photocurrent of a photodiode in each channel is removed in predetermined charge packets provided by a dumping circuit and the binary encoded number of delivered charge packets corresponds to the actual photocurrent. Charge balance photodiode arrays have a wide variety of applications. It is therefore useful to adapt photodiode arrays to the specific requirements of an individual application. The intention therefore provides a photodiode array having at least one switching circuit to vary signal processing parameters such as a gain factor g or an attenuation factor k. This improvement facilitates a multifunctional photodiode array for a plurality of different applications.

Claims

1. A photodiode array having a plurality of channels, each channel comprising:

a photodiode which is reverse biased such that it acts as a current source and which provides an electrical output signal in response to the light impinging on said photodiode,

a signal processing unit for processing said electrical output signal of the photodiode, and

an A/D conversion circuit for providing a digital output signal indicative of the intensity of light impinging on said photodiode, comprising;

an integrator circuit for accumulating a charge corresponding to said photodiode output signal, said integrator circuit having an output signal corresponding to an accumulated charge;

a controllable dumping circuit, coupled to an input of said integrator circuit, for dumping a number of predefined charge packets to or from said integrator circuit;

a comparator circuit for comparing the output signal of the integrator circuit with a predetermined signal;

a logic circuit, connected to an output of said comparator circuit and to a control input of said dumping circuit for controlling said charge dump packets to keep the output signal of the integrator circuit within a predetermined range about said predetermined signal, and

a digital counter for counting the number of charge packets to or from the integrator circuit during a predetermined time interval,

wherein said number of charge packets depends on at least one system-specific parameter comprising the time interval for accumulating the charge packets, the value of said charge packets, or the value of said predetermined signal for comparison to the output signal of the integrator circuit,

and further wherein, said photodiode array comprises a switching circuit to vary said at least one system-specific parameter for adapting the photodiode array to different applications,

wherein said switching circuit comprises in said dumping circuit, a plurality of capacitors selectively connected together by a plurality of switches for

programmably varying the effective capacitance of said dumping circuit.

2. Photodiode array as in claim 1, wherein said switching circuit is programmable.

3. Photodiode array as in claim 2, wherein said switching circuit is effected using CMOS-technology.

4. Photodiode array as in claim 1, wherein said switching circuit comprises an interval control circuit having an output signal determining the length of said time interval.

5. Photodiode array as in claim 4, wherein said interval control circuit comprises a controllable shift register to adjust said time interval, and further wherein said dumping circuit comprises a plurality of capacitors selectively connected together by a plurality of switches for providing fixed charge dumps of a fixed frequency to or from said integrator circuit.

6. Photodiode array as in claim 1, wherein said switching circuit comprises a controllable current amplifier, functioning as a current mirror, connected between the photodiode and the integrator circuit.

7. Photodiode array as in claim 6, wherein said current amplifier is effected by CMOS-technology, wherein at least two current amplifier stages are connected in series to provide a multistage current amplifier.

8. Photodiode array as in claim 7, wherein at least one additional FET is switched in parallel or in series with an input of said current amplifier in at least one of said amplifier stages.

9. Photodiode array as in claim 8, wherein said at least two current amplifier stages connected in series comprise a first current amplification stage further comprising an output channel connected in parallel to a drain terminal and a gate terminal of a first FET, and to a gate terminal of a second FET, wherein said first and second FETs comprise a second current amplification stage.

10. Photodiode array as in claim 8, comprising a plurality of multistage current amplifiers connected in parallel, wherein each of said plurality of multistage current amplifiers provides an output current, wherein each of said output currents are summed to form one common input current for at least one additional current amplification stage common to each of said plurality of multistage current amplifiers.

11. The photodiode array of claim 1, wherein said group of system specific parameters further comprises the time interval utilized by said integrator circuit for accumulating said charge.

12. The photodiode array of claim 7, wherein at least one additional FET is switched in parallel or in series with an output of said current amplifier in at least one of said amplifier stages.

13. A photodiode array having a plurality of channels, each channel comprising:

a photodiode which is reverse biased such that it acts as a current source and which provides an electrical output signal in response to the light impinging on said photodiode;

a controllable current amplifier, coupled to said photodiode output signal; and

an A/D conversion circuit for providing a digital output signal indicative of the intensity of light impinging on said photodiode, which comprises;

an integrator circuit for accumulating a charge corresponding to said photodiode output signal, said integrator circuit having an output signal corresponding to an accumulated charge;

a controllable dumping circuit, coupled to an input of said integrator circuit, for dumping a number of predefined charge packets to or from said integrator circuit;

a comparator circuit for comparing the output signal of the integrator circuit with a predetermined signal;

a logic circuit, connected to an output of said comparator circuit and to a control input of said dumping circuit for controlling said charge dump packets to keep the output signal of the integrator circuit within a predetermined range about said predetermined signal; and

a digital counter for counting the number of charge packets to or from the integrator circuit during a predetermined time interval,

wherein said number of charge packets depends on at least one system-specific parameter comprising the time interval for accumulating the charge packets, the value of said charge packets, or the value of said predetermined signal for comparison to the output signal of the integrator circuit,

and further wherein, said photodiode array comprises a switching circuit to vary said at least one system-specific parameter for adapting the photodiode array to different applications,

wherein said switching circuit comprises in said controllable current amplifier;

a first current amplification stage further comprising an output channel connected in parallel to a drain terminal and a gate terminal of a first FET, and to a gate terminal of a second FET, wherein said first and second FETs comprise a second current amplification stage having a second stage output; and

at least one additional FET switched in parallel or in series with an input of said current amplifier in at least one of said amplifier stages;

wherein a plurality of said first and second amplification stages are connected in parallel, such that each of said second stage outputs are summed to form a common input current for at least one additional current amplification stage common to each of said plurality of first and second amplification stages.

14. The photodiode array of claim 13 wherein said controllable dumping circuit comprises a plurality of capacitors selectively connected together by a plurality of switches for programmably varying the effective capacitance of said dumping circuit.