Backside bus vias

• US 6,300,670 B1
• Filed: 07/26/1999
• Issued: 10/09/2001
• Est. Priority Date: 07/26/1999
• Status: Expired due to Term

• Current Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Original Assignee: STMicroelectronics Incorporated (STMicroelectronics NV)
• Inventors: Thomas, Danielle A., Kramer, Alan H.
• Primary Examiner(s): Tran, Minh Loan
• Assistant Examiner(s): THAI, LUAN C
• Application Number:
  US09/360,836
• Time in Patent Office: 806 Days
• Field of Search: 257/621, 257/698, 257/774, 257/772, 257/773, 257/780, 257/777, 257/779, 257/680
• US Class Current: 257/621
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/05568 the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05573 Single external layer
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 Potassium [K]

Abstract

Metal taps for bus conductors are formed within an active layer, within one or more of the metallization levels, on the active side of a substrate in the area of a bus via. Alignment marks are formed in the same metallization level, in the same area. A slot is then blind etched from the backside of the substrate, exposing the metal taps and the alignment marks. The slot is etched, using an oxide or nitride hard mask, into the backside surface of the substrate with significantly sloped sidewalls, allowing metal to be deposited and patterned on the backside. An insulating layer and deposited metal on the backside surface of the substrate may require a blind etch to expose alignment marks, if any, but front-to-back alignment precision utilizing the exposed alignment marks may permit much smaller design rules for both the metal tabs and the backside interconnects formed from the metal layer. Backside contact pads may also be formed from the metal layer. The backside bus via slot may be etched in the body of a die, near a central region, or along the die boundary to form a shared backside bus via in which metal tabs on opposite sides of the slot connect to backside contacts on different dice after separation of the dice along the boundary. The backside bus is beneficial for sensor devices, leaving more room for sensor circuitry on the active side and simplifying packaging, for pad-limited designs, and for forming stackable integrated circuits.

Claims

1. An integrated circuit structure, comprising:

a substrate having an active layer including a plurality of bus taps within a metallization level within the active layer;

a slot in a backside surface of the substrate exposing the bus taps; and

a plurality of interconnects in the slot, each interconnect electrically connecting a single bus tap within the plurality of bus taps to a contact pad within a plurality of contact pads on the backside surface of the substrate.

2. The integrated circuit structure of claim 1, wherein the plurality of bus taps are within a first metallization level within the active layer.

3. The integrated circuit structure of claim 1, wherein the plurality of bus taps include a first set of bus taps on a first side of a logical boundary between two integrated circuit die and a second set of bus taps on a second side of the logical boundary.

4. The integrated circuit structure of claim 1, wherein the slot has sidewalls sloped at an angle of 54.7°

.

5. The integrated circuit structure of claim 4, wherein the slot is formed using a KOH based etch in <

100>

silicon.

6. The integrated circuit structure of claim 1, wherein the slot has a width at a bottom of the slot exceeding a kerf of a device employed to separate two die including the slot plus twice a required contact area.

7. The integrated circuit structure of claim 1, wherein the slot has portions on both sides of a logical boundary between two integrated circuit die.

8. The integrated circuit structure of claim 1, further comprising:

a dielectric on sidewalls in the slot and on the backside surface of the substrate between the substrate and the plurality of interconnects and between the substrate and the plurality of backside contact pads.

9. The integrated circuit structure of claim 1, wherein the plurality of bus taps are connects to a first integrated circuit within a first die and a second integrated circuit within a second die.

10. The integrated circuit structure of claim 1, wherein the plurality of bus taps include first and second sets of bus taps on opposite sides of the slot, wherein the first set of bus taps is connected to a first integrated circuit within a first die and the second set of bus taps is connected to a second integrated circuit within a second die.

11. A circuit structure, comprising:

a substrate die containing an integrated circuit within an active layer including a plurality of bus taps, the plurality of bus taps within a metallization level within the active layer and connected to the integrated circuit;

a slot in a backside surface and along an edge of the substrate die, wherein portions of the bus taps are exposed at a bottom of the slot; and

a plurality of interconnects in the slot and on the backside surface, each interconnect connecting a single bus tap within the plurality of bus taps to a contact pad within a plurality of contact pads on the backside surface of the substrate die.

12. The circuit structure of claim 11, wherein the plurality of bus taps extend to the edge of the substrate die.

13. The circuit structure of claim 11, wherein the plurality of bus taps extend into the slot but not to the edge of the substrate die.

14. The circuit structure of claim 11, wherein the slot has sidewalls sloped at an angle of 54.7°

.

15. The circuit structure of claim 11, wherein the substrate die comprises a first substrate die and the integrated circuit comprises a first integrated circuit, the circuit structure further comprising:

a second substrate die containing a second integrated circuit stacked with the substrate die, wherein the plurality of backside contact pads on the first substrate die are electrically connected to contacts on the second substrate die which are connected to the second integrated circuit.

16. The circuit structure of claim 15, wherein the connection between the plurality of backside contact pads on the first substrate die and the contacts on the second substrate die form a bus.

17. The circuit structure of claim 15, wherein the connection between the plurality of backside contact pads on the first substrate die and the contacts on the second substrate die daisy chain the first and second integrated circuits.

18. An integrated circuit structure, comprising:

a substrate including first and second die separated by a logical boundary, each die containing an integrated circuit within an active layer and including a plurality of bus taps within a metallization level for the active layer which are connected to the integrated circuit;

a slot in a backside surface along the logical boundary, wherein portions of the bus taps are exposed at a bottom of the slot; and

a plurality of interconnects in the slot and on the backside surface, each interconnect connecting a single bus tap within the plurality of bus taps to a contact pad within a plurality of contact pads on the backside surface of the substrate.

19. The integrated circuit structure of claim 18, wherein the slot has sidewalls sloped at an angle formed using a KOH based etch in <

100>

silicon.

20. The integrated circuit structure of claim 18, wherein the slot has a width at a bottom of the slot exceeding a kerf of a device employed to separate the first and second die plus twice a required contact area.