Wafer test method with probe card having on-board multiplex circuitry for expanding tester resources

• US 6,300,786 B1
• Filed: 10/18/1999
• Issued: 10/09/2001
• Est. Priority Date: 05/11/1998
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman, Doherty, C. Patrick, deVarona, Jorge L.
• Primary Examiner(s): Brown, Glenn W.
• Assistant Examiner(s): Hamdan, Wasseem H.
• Application Number:
  US09/420,256
• Time in Patent Office: 722 Days
• Field of Search: 324/765, 324/754, 324/537, 324/158.1, 438/6, 298/30, 298/74, 298/82, 298/29
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 1/07385 using switching of signals between probe tips and test bed, i.e. the standard contact matrix which in its turn connects to the tester
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: Y10T 29/49124 On flat or curved insulated base, e.g., printed circuit, etc.
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49204 Contact or terminal manufacturing
• CPC Class Codes: Y10T 29/49218 with deforming

Abstract

A probe card, a test method and a test system for testing semiconductor wafers are provided. The test system includes the probe card, a tester for generating test signals, and a wafer prober for placing the wafers and probe card in physical contact. The probe card includes contacts for electrically engaging die contacts on the wafer. The probe card also includes an on board multiplex circuit adapted to fan out and selectively transmit test signals from the tester to the probe card contacts. The multiplex circuit expands tester resources by allowing test signals to be written to multiple dice in parallel. Reading of the dice can be performed in groups up to the limit of the tester resources. In addition to expanding tester resources, the multiplex circuit maintains the individuality of each die, and permits defective dice to be electrically disconnected.

Claims

1. A method for testing a semiconductor wafer containing a plurality of dice having a plurality of die contacts comprising:

providing a tester configured to transmit test signals to the dice on the wafer;

providing a probe card comprising a plurality of probe card contacts in electrical communication with the tester, the probe card contacts arranged in sets configured to electrically engage selected dice on the wafer;

providing a multiplex circuit on the probe card in electrical communication with the probe card contacts and configured to selectively enable and disable the probe card contacts;

placing the probe card contacts in electrical communication with the die contacts on the wafer; and

using the multiplex circuit to control the test signals to fan out the test signals to the probe card contacts, to selectively transmit the test signals to the die contacts while the sets maintain a uniqueness of each die, and to disconnect defective dice.

2. The method of claim 1 wherein the probe card contacts comprise raised members at least partially covered with conductive layers.

3. The method of claim 1 wherein the probe card comprises silicon and the probe card contacts comprise etched members having projections configured to penetrate the die contacts.

4. The method of claim 1 wherein the probe card contacts comprise microbumps on a polymer film attached to the probe card.

5. The method of claim 1 wherein the die contacts comprise solder bumps, and the probe card contacts comprise indentations at least partially covered with conductive layers and configured to retain and electrically engage the solder bumps.

6. A method for testing a semiconductor wafer containing a plurality of dice having a plurality of die contacts comprising:

providing a tester configured to transmit a write test signal to the dice;

providing a probe card comprising a plurality of probe card contacts in electrical communication with the tester, the probe card contacts arranged in sets configured to maintain a uniqueness of each die on the wafer;

providing a multiplex circuit on the probe card configured to control the test signals to fan out the write test signal into multiple write test signals and to selectively enable or disable the probe card contacts;

placing the probe card contacts in electrical communication with selected die contacts on the wafer;

writing the multiple write test signals to at least some of the selected die contacts at a same time by selective actuation of the probe card contacts;

reading a plurality of read test signals from the selected die contacts in groups by selective actuation of the probe card contacts; and

disabling at least some of the probe card contacts to disconnect any defective dice.

7. The method of claim 6 wherein the probe card comprises a semiconductor substrate and the multiplex circuit comprises a plurality of integrated circuits on the substrate.

8. The method of claim 6 further comprising providing a controller in electrical communication with the multiplex circuit configured to transmit control signals for controlling the multiplex circuit.

9. A method for testing semiconductor dice contained on a wafer comprising:

providing a tester comprising a test circuitry configured to generate and transmit write test signals to the dice and to analyze read test signals from the dice, the tester having tester resources determined by a signal generating, transmitting and analyzing capability of the test circuitry;

providing a probe card comprising an on-board multiplex circuit and a plurality of probe card contacts in electrical communication with the multiplex circuit and the tester, the mulitplex circuit configured to control the test signals to speed up the testing, by fanning out the write test signals to multiple dice, and by reading the read test signals in groups up to a limit of the tester resources;

placing the probe card contacts in electrical communication with die contacts on selected dice;

writing the write test signals to the selected dice at a same time; and

reading the read test signals from the selected dice.

10. The method of claim 9 further comprising testing the die contacts on the selected dice for opens and shorts prior to the writing step.

11. The method of claim 9 further comprising following the reading step, disconnecting a defective die of the selected dice from the tester using the multiplex circuit.

12. A method for testing semiconductor dice contained on a water having a plurality of die contacts comprising;

providing a tester having a signal writing capability and a signal reading capability;

providing a probe card comprising a multiplex circuit and a plurality of probe card contacts in electrical communication with the multiplex circuit and the tester;

placing the probe card contacts in electrical communication with the die contacts on selected dice; and

using the multiplex circuit to control the test signals to expand the signal writing capability of the tester, and to speed up the testing, by multiplexing write test signals from the tester to the die contacts on the selected dice, by reading read test signals from the selected dice in groups up to the signal reading capability, and by controlling the probe card contacts to disable defective dice.

13. The method of claim 12 further comprising prior to the using step, testing the dice for opens and shorts in groups.

14. The method of claim 12 wherein the probe card comprises a silicon substrate and the multiplex circuit comprises a plurality of integrated circuits on the silicon substrate.

15. The method of claim 12 wherein the probe card contacts comprise projections configured to penetrate the die contacts.

16. The method of claim 12 wherein the die contacts comprise bumps and the probe card contacts comprise indentations configured to retain the bumps.