Scanning circuit for driving liquid crystal display

• US 6,300,928 B1
• Filed: 07/09/1998
• Issued: 10/09/2001
• Est. Priority Date: 08/09/1997
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Electronics, Inc. (LG Corporation)
• Inventors: Kim, Young Dae
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): NGUYEN, FRANCIS N
• Application Number:
  US09/112,208
• Time in Patent Office: 1,188 Days
• Field of Search: 345/92, 345/90, 345/98, 345/100, 345/204, 345/197, 345/58, 377/75, 377/64, 377/78-79
• US Class Current: 345/92
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/184 with field-effect transistors, e.g. MOS-FET
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence

Abstract

A scanning circuit that can minimize the number of input signals and switch signals applied to row lines of a liquid crystal panel, and reduce deterioration of a circuit is disclosed. The circuit includes input signal lines and a plurality of substantially identical stages cascade-connected to the input signal lines to produce a plurality of phase delayed scanning signals. Each stage has an input terminal and an output terminal. Also, each stage is provided with output circuitry comprising a push-pull amplifier including pull-up and pull-down transistors having respective conduction paths connected in series with the output terminal thereof and respective control electrodes, the push-pull amplifier having a supply terminal for applying one of the phase delayed scanning signals, input circuitry responsive to scanning pulse applied to the input terminal for generating first and second control signals which are coupled to the control electrodes of the pull-up and pull-down transistors for conditioning the push-pull amplifier to provide output scanning pulses, and means for raising a voltage of the first control signal to be applied to the control electrode of the pull-up transistor.

Claims

1. A scanning circuit comprising a plurality of cascaded scanning stages, each of the scanning stages having an input terminal and an output terminal, the scanning circuit including means for generating phase delayed scanning signals and means for receiving an input signal, the scanning stages comprising:

output circuitry comprising a push-pull amplifier including a pull-up transistor and a pull-down transistor having respective conduction paths connected in series with the output terminal, the pull-up transistor having a control electrode and the pull-down transistor having a control electrode, the push-pull amplifier having a supply terminal for receiving one of the phase delayed scanning signals;

input circuitry responsive to a scanning pulse applied to the input terminal for generating first and second control signals that are respectively coupled to the control electrodes of the pull-up transistor and a pull-down transistor for conditioning the push-pull amplifier to provide output scanning pulses; and

means responsive to a signal at the output terminal for raising a voltage of the first control signal to be applied to the control electrode of the pull-up transistor.

2. The scanning circuit as set forth in claim 1, wherein the input circuitry includes a first transistor having a conduction path connected to the control electrode of the pull-up transistor, and a control electrode and a first electrode that are connected to the input terminal;

and a second transistor having a conduction path coupled in series with the conduction path of the first transistor and connected to the control electrode of the pull-up transistor.

3. The scanning circuit as set forth in claim 2, wherein the input circuitry further includes a third transistor having a conduction path connected to the control electrode of the pull-down transistor and a control electrode connected to the input terminal;

and a fourth transistor having a conduction path coupled in series with the conduction path of the third transistor and the control electrode of the pull-down transistor, and a control electrode connected to the output terminal of a subsequent cascaded stage.

4. The scanning circuit as set forth in claim 3, further comprising means for supplementing a potential to the control electrode of the pull-down transistor periodically during a time interval at which the pull-up transistor is turned off.

5. The scanning circuit as set forth in claim 4, wherein the potential supplementing means includes a fifth transistor having a conduction path connected between the control electrode of the fourth transistor and the supply terminal, and a control electrode connected to the control electrode of the pull-down transistor.

6. The scanning circuit as set forth in claim 3, further comprising means for accelerating a turning-off speed of the pull-down transistor.

7. The scanning circuit as set forth in claim 6, wherein the accelerating means includes a fifth transistor having a conduction path coupled in parallel with the conduction path of the third transistor, and a control electrode connected to the control electrode of the pull-up transistor.

8. The scanning circuit as set forth in claim 7, wherein the accelerating means further includes a sixth transistor having a conduction path cascade-connected to the conduction path of the fifth transistor, and a control electrode connected to the conduction path of the fifth transistor.

9. The scanning circuit as set forth in claim 1, wherein the input circuitry includes a diode having a conduction path connected between the input terminal and the control electrode of the pull-up transistor, and an electrode connected to the input terminal;

and a transistor having a conduction path coupled in series with the conduction path of the diode and connected to the control electrode of the pull-up transistor.

10. The scanning circuit as set forth in claim 1, wherein the voltage raising means includes a capacitor connected to the output terminal and the control electrode of the pull-up transistor.

11. A scanning circuit comprising a plurality of cascaded scanning stages, each of the scanning stages having an input terminal and an output terminal, the scanning circuit including means for generating phase delayed scanning signals and means for receiving an input signal, the scanning stages comprising:

output circuitry comprising a push-pull amplifier including a pull-up transistor and a pull-down transistor having respective conduction paths connected in series with the output terminal and respective control electrodes, the push-pull amplifier having a supply terminal for receiving one of the phase delayed scanning signals;

input circuitry responsive to a scanning pulse applied to the input terminal for generating first and second control signals that are coupled to the control electrodes of the pull-up and pull-down transistors for conditioning the push-pull amplifier to provide output scanning pulses; and

means for accelerating a tuming-off speed of the pull-down transistor by discharging a voltage at the control electrode of the pull-down transistor selectively in one of two paths.

12. The scanning circuit as set forth in claim 11, wherein the input circuitry includes a first transistor having a conduction path connected to the control electrode of the pull-up transistor, and a control electrode and a first electrode that are connected to the input terminal;

and a second transistor having a conduction path coupled in series with the conduction path of the first transistor and connected to the control electrode of the pull-up transistor.

13. The scanning circuit as set forth in claim 12, wherein the input circuitry further includes a third transistor having a conduction path connected to the control electrode of the pull-down transistor and a control electrode connected to the input terminal;

and a fourth transistor having a conduction path coupled in series with the conduction path of the third transistor and the control electrode of the pull-down transistor, and a control electrode connected to the output terminal of one of the plurality of cascaded stages.

14. The scanning circuit as set forth in claim 13, further comprising means for supplementing a potential to the control electrode of the pull-down transistor periodically during a time interval at which the pull-up transistor is turned off.

15. The scanning circuit as set forth in claim 14, wherein the potential supplementing means includes a fifth transistor having a conduction path connected between the control electrode of the fourth transistor and the supply terminal, and a control electrode connected to the control electrode of the pull-down transistor.

16. The scanning circuit as set forth in claim 13, wherein the accelerating means includes a fifth transistor having a conduction path coupled in parallel with the conduction path of the third transistor, and a control electrode connected to the control electrode of the pull-up transistor.

17. The scanning circuit as set forth in claim 16, wherein the accelerating means further includes a sixth transistor having a conduction path cascade-connected to the conduction path of the fifth transistor, and a control electrode connected to the conduction path of the fifth transistor.

18. The scanning circuit as set forth in claim 11, wherein the input circuitry includes a diode having a conduction path connected between the input terminal and the control electrode of the pull-up transistor, and an electrode connected to the input terminal;

and a transistor having a conduction path coupled in series with the conduction path of the diode and connected to the control electrode of the pull-up transistor.

19. A scanning circuit comprising a plurality of cascaded scanning stages, each of said scanning stages having an input terminal and an output terminal, the scanning circuit including means for generating phase delayed scanning signals and means for receiving an input signal, the scanning stages comprising:

output circuitry comprising a push-pull amplifier including a pull-up transistor and a pull-down transistor having respective conduction paths connected in series with the output terminal and respective control electrodes, the push-pull amplifier having a supply terminal for receiving one of the phase delayed scanning signals;

input circuitry responsive to a scanning pulse applied to the input terminal for generating first and second control signals that are coupled to the control electrodes of the pull-up and pull-down transistors for conditioning the push-pull amplifier to provide output scanning pulses; and

means for supplementing a potential to the control electrode of the pull-down transistor during a time interval at which the pull-up transistor is turned off.

20. The scanning circuit as set forth in claim 19, wherein the input circuitry includes a first transistor having a conduction path connected to the control electrode of the pull-up transistor, and a control electrode and a first electrode that are connected to the input terminal;

and a second transistor having a conduction path coupled in series with the conduction path of the first transistor and connected to the control electrode of the pull-up transistor.

21. The scanning circuit as set forth in claim 20, wherein the input circuitry further includes a third transistor having a conduction path connected to the control electrode of the pull-down transistor and a control electrode connected to the input terminal;

and a fourth transistor having a conduction path coupled in series with the conduction path of the third transistor and the control electrode of the pull-down transistor, and a control electrode connected to the output terminal of a subsequent cascaded stage.

22. The scanning circuit as set forth in claim 21, further comprising means for accelerating a turning-off speed of the pull-down transistor.

23. The scanning circuit as set forth in claim 22, wherein the accelerating means includes a fifth transistor having a conduction path coupled in parallel with the conduction path of the third transistor, and a control electrode connected to the control electrode of the pull-up transistor.

24. The scanning circuit as set forth in claim 23, wherein the accelerating means further includes a sixth transistor having a conduction path cascade-connected to the conduction path of the fifth transistor, and a control electrode connected to the conduction path of the transistor.

25. The scanning circuit as set forth in claim 19, wherein the input circuitry includes a diode having a conduction path connected between the input terminal and the control electrode of the pull-up transistor, and an electrode connected to the input terminal;

and a transistor having a conduction path coupled in series with the conduction path of the diode and connected to the control electrode of the pull-up transistor.

26. The scanning circuit as set forth in claim 21, wherein the potential supplementing means includes a fifth transistor having a conduction path connected between the control electrode of the fourth transistor and the supply terminal, and a control electrode connected to the control electrode of the pull-down transistor.