Three-phase current sensor and estimator

• US 6,301,137 B1
• Filed: 11/03/2000
• Issued: 10/09/2001
• Est. Priority Date: 11/05/1999
• Status: Expired due to Fees

• Current Assignee: Hui Li
• Original Assignee: Hui Li
• Inventors: Li, Hui
• Primary Examiner(s): NGUYEN, MATTHEW VAN
• Application Number:
  US09/706,135
• Time in Patent Office: 340 Days
• Field of Search: 363/40, 363/41, 363/56.01, 363/56.02, 363/97, 363/98, 363/131, 363/132, 318/254, 318/439, 318/800, 318/801, 318/802, 318/803
• US Class Current: 363/98
• CPC Class Codes: H02M 1/0009 Devices or circuits for detecting current in a converter
• CPC Class Codes: H02M 7/53873 with digital control

Abstract

In a three-phase DC-to-AC inverter including, for driving each leg of the load, a controlled power driver such a pulse-width modulated field-effect transistor (FET) or insulated gate bipolar transistor (IGBT) pair, an estimator for estimating the current in each leg of the load. A low-resistance leg resistor is connected in series in the lower leg of each transistor pair. The voltages across the leg resistors are applied to two differential amplifiers to generate two discrete voltage difference values that are transmitted to an estimator. The estimator solves specified differential equations using suitably interconnected combiners, integrators, amplifiers and multipliers, or discrete digital equivalent or programmed computer equivalent, to derive a value for the estimated current in each leg of the load.

Claims

1. A leg current estimator combination for estimating the load current in each of the legs A, B and C of a three-phase load, each leg being driven by a controlled power driver such as a pulse-width modulated field-effect transistor (FET) pair or insulated gate bipolar transistor (IGBT) pair, comprising:

a) a low-resistance leg resistor in each leg of the load and means for deriving the voltage across each said resistor;

b) a first differential amplifier receiving as its two inputs the voltage across the resistors for legs A and C of the load and producing a first analog output signal representing the difference between the two inputs thereto;

c) a second differential amplifier receiving as its two inputs the voltage across the resistors for legs B and C of the load and producing a second analog output signal representing the difference between the two inputs thereto;

d) a first analog/digital converter for converting the output of the first differential amplifier to a digital signal;

e) a second analog/digital converter for converting the output of the second differential amplifier to a digital signal;

f) a leg A output circuit comprising in series a leg A output combiner receiving as a first input the output of the first analog/digital converter, a leg A integrator for integrating the output of the leg A combiner, and a leg A output amplifier for providing an output signal representing the estimated leg A load current;

g) a leg C output circuit comprising in series a leg C output combiner receiving as a first input the output of the second analog/digital converter, a leg C integrator for integrating the output of the leg C combiner, and a leg C output amplifier for providing an output signal representing the estimated leg C load current;

h) an intermediate combiner receiving as a first input the output of the first analog/digital converter and receiving as a second input the output of the second analog/digital converter and producing an intermediate output signal representing the difference between the two input signals thereto;

i) a leg B output circuit comprising in series a leg B output combiner receiving as a first input the intermediate output signal, a leg B integrator for integrating the output of the combiner, and a leg B output amplifier for providing an output signal representing the estimated leg B load current;

j) a leg A feedback loop comprising a leg A multiplier and a leg A feedback combiner connected in series, the leg A multiplier receiving as a first input the output of the leg A output amplifier and as a second input a signal representing the value (M−

α

)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg A multiplier, said multiplier output signal being fed as a first input to the leg A feedback combiner;

k) a leg B feedback loop comprising a leg B multiplier and a leg B feedback combiner connected in series, the leg B multiplier receiving as a first input the output of the leg B output amplifier and as a second input a signal representing the value (M−

β

)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg B multiplier, said multiplier output signal being fed as a first input to the leg B feedback combiner;

l) a leg C feedback loop comprising a leg C multiplier and a leg C feedback combiner connected in series, the leg C multiplier receiving as a first input the output of the leg C output amplifier and as a second input a signal representing the value (M−

γ

)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg C multiplier, said multiplier output signal being fed as a first input to the leg C feedback combiner;

the leg A feedback combiner receiving as a second input the output of the leg C multiplier, and producing an output signal representing the difference between the two inputs thereto;

the leg B feedback combiner receiving as a second input the output of the leg A multiplier, and producing an output signal representing the difference between the two inputs thereto;

the leg C feedback combiner receiving as a second input the output of the leg B multiplier, and producing an output signal representing the difference between the two inputs thereto;

the leg A output combiner receiving as a second input the output of the leg A feedback combiner with optional amplification and producing as the leg A output combiner signal the difference between the two inputs thereto;

the leg B output combiner receiving as a second input the output of the leg B feedback combiner with optional amplification and producing as the leg B output combiner signal the difference between the two inputs thereto;

the leg C output combiner receiving as a second input the output of the leg C feedback combiner with optional amplification and producing as the leg C output combiner signal the negative of the sum of the two inputs thereto;

wherein

each of the leg A, leg B and leg C combiners produces a respective output signal value u_A, u_B, or u_C (each value generically referred to as “

u”

);

each of the integrators processes its associated input signal value u to produce an output signal value $y=\frac{1}{s}<br><br>\text{\hspace{1em}<br><br>}<br><br>u,$

where s is the Laplace operator;

each of the leg A, leg B and leg C output amplifiers has a gain z;

M is the half-period of the pulse-width modulation carrier signal;

and the values α

, β and

γ

are derived from the equations

2. A combination according to claim 1, wherein selected ones of elements (b) through (l) are embodied within a microprocessor operational to perform the functions of said selected elements.

3. A combination according to claim 1, wherein the optional amplification of the output of each said feedback combiner provides a voltage gain of 1.

4. A combination according to claim 1, wherein the low-resistance leg resistors are respectively located in the return legs of the load between their respective associated controlled power driver and ground, and the differential amplifiers are connected between the higher-voltage terminal of their respective associated low-resistance leg resistors and ground.

5. A combination according to claim 4, wherein selected ones of elements (b) through (l) are embodied within a microprocessor operational to perform the functions of said selected elements.

6. A combination according to claim 1, wherein the differential amplifiers each have a selected gain K and a frequency response represented by the dimensionless value 1/(TS+1), T being the inherent time constant of each of the differential amplifiers, and S being the Laplace operator, whereby the output D_vac of the first differential amplifier is

7. A combination according to claim 6, wherein selected ones of elements (b) through (l) are embodied within a microprocessor operational to perform the functions of said selected elements.

8. A combination according to claim 6, wherein the gain z represents the dimension-less bandwidth of the signal processing circuit and is selected so that computation performed by the signal processor occurs within the range of linear performance of the load.

9. A combination according to claim 8, wherein selected ones of elements (b) through (l) are embodied within a microprocessor operational to perform the functions of said selected elements.

10. A combination according to claim 8, wherein the leg resistors are of substantially identical resistance and the differential amplifiers are selected for substantially identical gain and internal time constant.

11. A combination according to claim 10, wherein selected ones of elements (b) through (l) are embodied within a microprocessor operational to perform the functions of said selected elements.

12. A combination according to claim 10, wherein the microcontroller provides pulse-width modulation control signals for the FETs and provides signals representing values α

, β

, γ

, M and z.

13. A combination according to claim 12, wherein selected ones of elements (b) through (l) are embodied within a microprocessor operational to perform the functions of said selected elements.

14. An estimator combination for estimating the load current in each of the legs A, B and C of a three-phase load, each leg being driven by a controlled power driver, comprising:

a) a low-resistance leg resistor in each leg of the load and means for deriving the voltage across each said resistor;

b) first differential means for producing a first differential digital signal representing the voltage difference between the voltages across the low-resistance leg resistors of legs A and C of the load;

c) second differential means for producing a second differential digital signal representing the voltage difference between the voltages across the low-resistance leg resistors of legs B and C of the load;

d) a leg A output circuit comprising in series a leg A output combiner receiving as a first input the first differential digital signal, a leg A integrator for integrating the output of the leg A combiner, and a leg A output amplifier for providing an output signal representing the estimated leg A load current;

e) a leg C output circuit comprising in series a leg C output combiner receiving as a first input the second differential digital signal, a leg C integrator for integrating the output of the leg C combiner, and a leg C output amplifier for providing an output signal representing the estimated leg C load current;

f) an intermediate combiner receiving as a first input the first differential digital signal and receiving as a second input the second differential digital signal and producing an intermediate output signal representing the difference between the two input signals thereto;

g) a leg B output circuit comprising in series a leg B output combiner receiving as a first input the intermediate output signal, a leg B integrator for integrating the output of the combiner, and a leg B output amplifier for providing an output signal representing the estimated leg B load current;

h) a leg A feedback loop comprising a leg A multiplier and a leg A feedback combiner connected in series, the leg A multiplier receiving as a first input the output of the leg A output amplifier and as a second input a signal representing the value (M−

α

)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg A multiplier, said multiplier output signal being fed as a first input to the leg A feedback combiner;

i) a leg B feedback loop comprising a leg B multiplier and a leg B feedback combiner connected in series, the leg B multiplier receiving as a first input the output of the leg B output amplifier and as a second input a signal representing the value (M−

β

)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg B multiplier, said multiplier output signal being fed as a first input to the leg B feedback combiner;

j) a leg C feedback loop comprising a leg C multiplier and a leg C feedback combiner connected in series, the leg C multiplier receiving as a first input the output of the leg C output amplifier and as a second input a signal representing the value (M−

γ

)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg C multiplier, said multiplier output signal being fed as a first input to the leg C feedback combiner;

the leg A feedback combiner receiving as a second input the output of the leg C multiplier, and producing an output signal representing the difference between the two inputs thereto;

the leg B feedback combiner receiving as a second input the output of the leg A multiplier, and producing an output signal representing the difference between the two inputs thereto;

the leg C feedback combiner receiving as a second input the output of the leg B multiplier, and producing an output signal representing the difference between the two inputs thereto;

the leg A output combiner receiving as a second input the output of the leg A feedback combiner with optional amplification and producing as the leg A output combiner signal the difference between the two inputs thereto;

the leg B output combiner receiving as a second input the output of the leg B feedback combiner with optional amplification and producing as the leg B output combiner signal the difference between the two inputs thereto;

the leg C output combiner receiving as a second input the output of the leg C feedback combiner with optional amplification and producing as the leg C output combiner signal the negative of the sum of the two inputs thereto;

wherein

each of the leg A, leg B and leg C combiners produces a respective output signal value u_A, u_B or u_C (each value generically referred to as “

u”

);

each of the integrators processes its associated input signal value u to produce an output signal value $y=\frac{1}{s}<br><br>\text{\hspace{1em}<br><br>}<br><br>u,$

where s is the Laplace operator;

each of the leg A, leg B and leg C output amplifiers has a gain z;

M is the half-period of the pulse-width modulation carrier signal; and

the values α

, β and

γ

are derived from the equations

15. A combination according to claim 14, wherein selected ones of elements (b) through (j) are embodied within a microprocessor operational to perform the functions of said selected elements.

16. A three-phase DC-to-AC inverter, including three pairs of FET transistors and control means to pulse-width modulate said transistors, comprising:

(a) an estimator combination for deriving the estimated current in each of the legs A, B and C of the load, said estimator comprising;

(i) first, second and third low-resistance leg resistors in respective return legs of each pair of transistors;

(ii) first and second differential amplifiers;

(iii) means to apply the voltage appearing at the junction of the return leg of the first pair of transistors and the associated first resistor to a first terminal of said first differential amplifier;

(iv) means to apply the voltage appearing at the junction of the return leg of the third pair of transistors and the associated third resistor to a second terminal of said first differential amplifier;

(v) means to apply the voltage appearing at the junction of the return leg of the second pair of transistors and the associated second resistor to a first terminal of said second differential amplifier; and

(vi) means to apply the voltage appearing at the junction of the return leg of the third pair of transistors and the associated third resistor to a second terminal of said second differential amplifier; and

(b) a signal processor to process the output signal D_vac of the first differential amplifier and the output signal D_vbc of the second differential amplifier;

where the output signal D_vac of the first differential amplifier is

17. An inverter according to claim 16, wherein the said signal processor processes the output signals D_vac, D_vbc of the differential amplifiers to solve the differential equations $\frac{}{}$

IaE

t

z

[DVac-IaEM

(M-α

)+IcEM

(M-γ

)];

$\frac{<br><br>I_{\mathrm{bE}}}{<br><br>t}=z<br><br>\left[D_{\mathrm{Vbc}}-D_{\mathrm{Vac}}+\frac{I_{\mathrm{aE}}}{M}<br><br>\left(M-\mathrm{\alpha <br><br>}\right)-\frac{I_{\mathrm{bE}}}{M}<br><br>\left(M-\mathrm{\beta <br><br>}\right)\right];<br><br>$$\frac{<br><br>I_{\mathrm{cE}}}{<br><br>t}=z<br><br>\left[-D_{\mathrm{Vbc}}+\frac{I_{\mathrm{bE}}}{M}<br><br>\left(M-\mathrm{\beta <br><br>}\right)-\frac{I_{\mathrm{bE}}}{M}<br><br>\left(M-\mathrm{\gamma <br><br>}\right)\right];<br><br>$

and

where

I_aE is the estimated current in leg A;

I_bE is the estimated current in leg B;

I_cE is the estimated current in leg C;

M is the half-period of the pulse-width modulation carrier signal; and

the values α

, β and

γ

are derived from the equations

18. An inventor according to claim 17, wherein the processor is a microprocessor operational to solve the said equations.

19. An estimator combination for estimating the load current in each of the legs A, B and C of a three-phase load, each leg being driven by a controlled power driver such as a pulse-width modulated field-effect transistor (FET) pair or insulated gate bipolar transistor (IGBT) pair, comprising:

a) a low-resistance leg resistor in each leg of the load and means for deriving the voltage across each said resistor;

b) a first differential amplifier receiving as its two inputs the voltage across the resistors for legs A and C of the load and producing an analog output signal representing the difference between the two inputs thereto;

c) a second differential amplifier receiving as its two inputs the voltage across the resistors for legs B and C of the load and producing an analog output signal representing the difference between the two inputs thereto;

d) a first analog/digital converter for converting the output of the first differential amplifier to a digital signal;

e) a second analog/digital converter for converting the output of the second differential amplifier to a digital signal;

f) a leg A output circuit comprising in series a leg A output combiner receiving as a first input the output of the first analog/digital converter, a leg A integrator for integrating the output of the leg A combiner, and a leg A output amplifier for providing an output signal representing the estimated leg A load current;

g) a leg C output circuit comprising in series a leg C output combiner receiving as a first input the output of the second analog/digital converter, a leg C integrator for integrating the output of the leg C combiner, and a leg C output amplifier for providing an output signal representing the estimated leg C load current;

h) an intermediate combiner receiving as a first input the output of the first analog/digital converter and receiving as a second input the output of the second analog/digital converter and producing an intermediate output signal representing the difference between the two input signals thereto;

i) a leg B output circuit comprising in series a leg B output combiner receiving as a first input the intermediate output signal, a leg B integrator for integrating the output of the combiner, and a leg B output amplifier for providing an output signal representing the estimated leg B load current;

j) a leg A feedback loop comprising a leg A multiplier and a leg A feedback combiner connected in series, the leg A multiplier receiving as a first input the output of the leg A output amplifier and as a second input a signal representing the value (M−

α

)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg A multiplier, said multiplier output signal being fed as a first input to the leg A feedback combiner;

k) a leg B feedback loop comprising a leg B multiplier and a leg B feedback combiner connected in series, the leg B multiplier receiving as a first input the output of the leg B output amplifier and as a second input a signal representing the value (M−

β

)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg B multiplier, said multiplier output signal being fed as a first input to the leg B feedback combiner;

l) a leg C feedback loop comprising a leg C multiplier and a leg C feedback combiner connected in series, the leg C multiplier receiving as a first input the output of the leg C output amplifier and as a second input a signal representing the value (M−

γ

)/M, and producing a multiplier output signal representing the product of the values of the first and second inputs to the leg C multiplier, said multiplier output signal being fed as a first input to the leg C feedback combiner;

the leg A feedback combiner receiving as a second input the output of the leg C multiplier, and producing an output signal representing the difference between the two inputs thereto;

the leg B feedback combiner receiving as a second input the output of the leg A multiplier, and producing an output signal representing the difference between the two inputs thereto;

the leg C feedback combiner receiving as a second input the output of the leg B multiplier, and producing an output signal representing the difference between the two inputs thereto;

the leg A output combiner receiving as a second input the output of the leg A feedback combiner with optional amplification and producing as the leg A output combiner signal the difference between the two inputs thereto;

the leg B output combiner receiving as a second input the output of the leg B feedback combiner with optional amplification and producing as the leg B output combiner signal the difference between the two inputs thereto;

the leg C output combiner receiving as a second input the output of the leg C feedback combiner with optional amplification and producing as the leg C output combiner signal the negative of the sum of the two inputs thereto;

wherein

each of the leg A, leg B and leg C combiners produces a respective output signal value u_A, u_B or u_C (each value generically referred to as “

u”

);

each of the integrators processes its associated input signal value u to produce an output signal value $y=\frac{1}{s}<br><br>\text{\hspace{1em}<br><br>}<br><br>u,$

 

where s is the Laplace operator;

each of the leg A, leg B and leg C output amplifiers has a gain z;

M is the half-period of the pulse-width modulation carrier signal; and

the values α

, β and

γ

are derived from the equations

20. An estimator according to claim 19, wherein the optional amplification of the output of each said feedback combiner provides a voltage gain of 1.

21. An estimator according to claim 20, in combination with a microcontroller for providing pulse-width modulation control signals for the controlled power driver and providing signals representative of values α

, β

, γ

, M and z.

22. An estimator according to claim 21, wherein selected ones of elements (b) through (l) are embodied within a microprocessor operational to perform the functions of said selected elements.

23. A combination for estimating the load current in each of three legs A, B, C of a three-phase load, each said leg being driven by a controlled power driver such as a pulse-width modulated field-effect transistor (FET) pair or insulated gate bipolar transistor (IGBT) pair, in response to pulse-width modulation provided by a microcontroller connected to the controlled power drivers;

wherein the microcontroller produces selected parameter signals representing the values of parameters α

, β

, γ

, M and z of the inverter;

comprising;

a) a low-resistance leg resistor in each leg of the load and means for deriving the voltage across each said resistor;

b) first differential means for producing a first differential digital signal representing the voltage difference between the voltages across the low-resistance leg resistors of legs A and C of the load;

c) second differential means for producing a second differential digital signal representing the voltage difference between the voltages across the low-resistance leg resistors of legs B and C of the load;

d) a signal processor for receiving the first and second differential digital signals and the selected parameter signals and processing said signals to derive an estimated current for each leg of the load;

where

the value M is the half-period of the pulse-width modulation carrier signal; and

the values α

, β and

γ

are derived from the equations

 

α

=V_L sin(ω

t−

Φ

)

24. A combination according to claim 23, wherein the signal processor is embodied within a microprocessor operational to perform the functions of said signal processor.

25. A combination for estimating the load current in each of three legs A, B, C of a three-phase load, each leg being driven by a controlled power driver such as a pulse-width modulated field-effect transistor (FET) pair or insulated gate bipolar transistor (IGBT) pair in response to pulse-width modulation provided by a microcontroller connected to the controlled power drivers;

wherein the microcontroller produces selected parameter signals representing the values of parameters α

, β

, γ

, M and z of the inverter;

comprising;

a) a low-resistance leg resistor in each leg of the load and means for deriving the voltage across each said resistor; and

b) a signal processor receiving (i) signals derived from the voltages across the low-resistance leg resistors and (ii) the selected parameter signals, and processing said signals to derive an estimated current for each leg of the load;

where

the value M is the half-period of the pulse-width modulation carrier signal; and

the values α

, β and

γ

are derived from the equations

26. A combination according to claim 25, wherein the signal processor solves the differential equations $\frac{}{}$

IaE

t=z

[DVac-IaEM

(M-α

)+IcEM

(M-γ

)];

$\frac{<br><br>I_{\mathrm{bE}}}{<br><br>t}=z<br><br>\left[D_{\mathrm{Vbc}}-D_{\mathrm{Vac}}+\frac{I_{\mathrm{aE}}}{M}<br><br>\left(M-\mathrm{\alpha <br><br>}\right)-\frac{I_{\mathrm{bE}}}{M}<br><br>\left(M-\mathrm{\beta <br><br>}\right)\right];<br><br>$$\mathrm{and}$$\frac{<br><br>I_{\mathrm{cE}}}{<br><br>t}=z<br><br>\left[-D_{\mathrm{Vbc}}+\frac{I_{\mathrm{bE}}}{M}<br><br>\left(M-\mathrm{\beta <br><br>}\right)-\frac{I_{\mathrm{cE}}}{M}<br><br>\left(M-\mathrm{\gamma <br><br>}\right)\right];<br><br>$

where

I_aE is the estimated current in leg A;

I_bE is the estimated current in leg B;

I_cE is the estimated current in leg C; and

t is time.

27. A combination according to claim 26, wherein the signal processor is embodied within a microprocessor operational to perform the functions of said signal processor.