Antifuse method to repair columns in a prefetched output memory architecture

• US 6,301,164 B1
• Filed: 08/25/2000
• Issued: 10/09/2001
• Est. Priority Date: 08/25/2000
• Status: Active Grant

• Current Assignee: Nanya Technology Corporation
• Original Assignee: Micron Technology, Inc.
• Inventors: Martin, Chris G., Manning, Troy A., Morgan, Donald M., Batra, Shubneesh
• Primary Examiner(s): Dinh, Son T.
• Application Number:
  US09/648,921
• Time in Patent Office: 410 Days
• Field of Search: 365/200, 365/225.7, 365/230.02, 365/189.02, 365/189.05, 365/189.12, 365/230.08
• US Class Current: 365/200
• CPC Class Codes: G11C 29/785 with redundancy programming schemes
• CPC Class Codes: G11C 29/812 using a reduced amount of fuses

Abstract

A memory device having a first set of programmable elements programmed to store an address of a column having a bad memory cell, and a second set of programmable elements programmed to store a segment-in-time (SIT) of the bad memory cell, the SIT of the bad memory cell indicating a relative position of the bad memory cell within a plurality of memory cells being accessed in a memory access. The SIT allows the memory device to selectively repair a bad memory cell within a column of memory cells accessed during a memory operation.

Claims

1. An integrated circuit comprising:

a first set of programmable elements programmed to store an address of a column having a bad memory cell; and

a second set of programmable elements programmed to store a segment-in-time (SIT) of the bad memory cell, the SIT of the bad memory cell indicating a relative position of the bad memory cell within a plurality of memory cells being accessed in a memory access.

2. The integrated circuit of claim 1 further comprising a match circuit connected to the first set of programmable elements, the match circuit producing a match signal when the column having the bad cell is accessed.

3. The integrated circuit of claim 1 further comprising a decode circuit connected to the second set of programmable elements, the decode circuit decoding a combination programmed in the second set of programmable elements and, upon receiving the match signal, producing a SIT signal indicating the SIT of the bad memory cell.

4. The integrated circuit of claim 1, wherein the first and second sets of programmable elements comprise antifuses.

5. The integrated circuit of claim 1, wherein the first and second sets of programmable elements comprise fuses.

6. An integrated circuit comprising:

a fuse logic having a first and a second group of programmable elements, the first group of programmable elements programmed to store an address of a column having a bad memory cell, the second group of programmable elements programmed to store a segment-in-time (SIT) information of the bad memory cell, the SIT information indicating a relative position of the bad memory cell within a plurality of memory cells being accessed in a previous memory access,

a SIT timing register connected to the fuse logic to receive the SIT information when the column having the bad cell is accessed, the SIT timing register holding the SIT information during a data transmission from the bad cell to a helper flip-flop sense amplifier (FF/SA) and releasing the SIT information after the data transmission to the helper FF/SA is completed.

7. The integrated circuit of claim 6 further comprising a match circuit connected to the first group of programmable elements, the match circuit producing a match signal when the column having the bad cell is accessed.

8. The integrated circuit of claim 6 further comprising a decode circuit connected to the second group of programmable elements, the decode circuit decoding a combination programmed in the second set of programmable elements and, upon receiving the match signal, producing a SIT signal indicating the SIT of the bad memory cell.

9. The integrated circuit of claim 6, wherein the first and second groups of programmable elements comprise antifuses.

10. The integrated circuit of claim 6, wherein the first and second groups of programmable elements comprise fuses.

11. The integrated circuit of claim 6, wherein the SIT timing register comprises a master latch to hold the SIT information and a slave latch to release the SIT information.

12. A memory device comprising:

storage cells and a redundant cell;

a plurality of helper flip-flop sense amplifiers (HFF/SA) connected to receive data the storage cells;

a redundant HFF/SA connected to receive data from the redundant cell;

a plurality of multiplexors connected to the HFF/SA and the redundant HFF/SA; and

a redundancy address match circuit connected to the multiplexors, the redundancy address match circuit having a plurality of SIT lines, each of the SIT lines is connected to a corresponding multiplexor, when one of the SIT lines transmits an SIT signal to the corresponding multiplexor, the corresponding multiplexor selects data from the redundant HFF/SA instead of data from the HFF/SA and outputs the data from redundant HFF/SA to an output of the corresponding multiplexor.

13. The memory device of claim 12, wherein the redundancy address match circuit further includes:

a first set of programmable elements programmed to store an address of a column having a bad memory cell; and

a second set of programmable elements programmed to store a segment-in-time (SIT) of the bad memory cell, the SIT of the bad memory cell indicating a relative position of the bad memory cell within a plurality of memory cells being accessed in a previous memory access.

14. A memory device comprising:

storage cells and redundant cells;

a read/write circuit connected to the storage cells;

a redundant read/write circuit connected to the redundant cells; and

a redundancy address match circuit connected to the read/write circuit and the redundant read/write circuit, the redundancy address match circuit comprising;

a first set of programmable elements programmed to store an address of a column having a bad memory cell; and

a second set of programmable elements programmed to store a segment-in-time (SIT) of the bad memory cell, the SIT of the bad memory cell indicating a relative position of the bad memory cell within a plurality of memory cells being accessed in a previous memory access.

15. The memory device of claim 14, wherein the memory further comprising a data read and a data write register connected to receive data from the read/write circuit.

16. The memory device of claim 15, wherein the data read register comprises a shift register, the shift register shifting data serially to an output buffer.

17. The memory device of claim 15, wherein the data read register comprises a plurality of data latches, the data latches shifting data in parallel to an output buffer.

18. The memory device of claim 14, wherein the redundancy address match circuit further includes a SIT timing register, the SIT timing register holding a SIT signal during a time before data from the storage cells arrives at the HFF/SA and transmitting the SIT signal to a multiplexor after the data from the storage cells arrives at the HFF/SA.

19. The memory device of claim 18, wherein the SIT timing register includes a master circuit to hold the SIT signal and a slave circuit to release the SIT signal.

20. A memory device comprising:

a read path including;

a plurality of digit lines connected to a column of storage cells;

a plurality of helper flip-flop sense amplifiers (HFF/SA) connected to the digit lines;

a plurality of multiplexors connected to the HFF/SA; and

a data read register connected to the multiplexors;

a redundant read path including;

a pair of redundant digit lines connected to a redundant cell;

a redundant helper flip-flop sense amplifier (HFF/SA) connected to the redundant digit lines;

a plurality of select lines connected to the multiplexors, wherein when the column is accessed and the column has a bad data bit from a storage cell, one of the select lines produces a segment-in-time (SIT) signal causing one of the multiplexors connecting to the HFF/SA which has the bad data bit to multiplex a data bit from the redundant HFF/SA instead of the bad data bit from one of the HFF/SA to the data read register.

21. The memory device of claim 20 further comprising a plurality of select transistors connected between the digit lines and the HFF/SA.

22. The memory device of claim 20 further comprising a plurality of redundant select transistors connected between the redundant digit lines and the redundant HFF/SA.

23. A memory device comprising:

storage cells and a redundant cell;

a plurality of write drivers connected to write data into the storage cells;

a redundant write driver connected to the redundant cell;

a plurality of multiplexors connected to the write drivers and the redundant write driver;

a data write register connected to the multiplexors; and

a redundancy address match circuit connected to the multiplexors, the redundancy address match circuit having a plurality of SIT lines, each of the SIT lines is connected to a corresponding multiplexor, when one of the SIT lines transmits an SIT signal to the corresponding multiplexor, the corresponding multiplexor routes data from the write data register to the redundant write driver.

24. The memory device of claim 23, wherein the redundancy address match circuit further includes:

a first set of programmable elements programmed to store an address of a column having a bad memory cell; and

a second set of programmable elements programmed to store a segment-in-time (SIT) of the bad memory cell, the SIT of the bad memory cell indicating a relative position of the bad memory cell within a plurality of memory cells being accessed in a previous memory access.

25. A system comprising:

a processor; and

a memory device connected to the processor, the memory device comprising;

storage cells and a redundant cell;

a plurality of helper flip-flop sense amplifiers (HFF/SA) connected to receive data the storage cells;

a redundant HFF/SA connected to receive data from the redundant cell;

a plurality of multiplexors connected to the HFF/SA and the redundant HFF/SA; and

a redundancy address match circuit connected to the multiplexors, the redundancy address match circuit having a plurality of SIT lines, each of the SIT lines is connected to a corresponding multiplexor, when one of the SIT lines transmits an SIT signal to the corresponding multiplexor, the corresponding multiplexor selects data from the redundant helper FF/SA instead of data from the helper FF/SA and outputs the data from redundant helper FF/SA to an output of the corresponding multiplexor.

26. A method of repairing a column of memory cells, the method comprising:

programming a first set of programmable elements to store an address of a column having a bad cell; and

programming a second set of programmable elements to store a segment-in-time (SIT) information of the bad cell indicating a relative position of the bad memory cell within a plurality of memory cells being accessed in a memory access,

decoding the SIT information to generate a SIT signal to replace the bad cell when the column having the bad cell is accessed.

27. The method of claim 26, wherein programming the first and second sets of programmable elements includes programming antifuses.

28. The method of claim 26, wherein programming the first and second sets of programmable elements includes programming fuses.

29. A method of reading a column of memory cells having a bad memory cell, the method comprising:

producing a segment-in-time (SIT) signal if an address of the column matches a programmed address during a memory access indicating the column has a bad cell;

transmitting data from the column of memory cells including data of the bad memory cell and data of a redundant cell to a plurality of multiplexors; and

transmitting the SIT signal to one of the multiplexors to cause the multiplexor to route the data of the redundant cell instead of the data of the bad cell to a data register.

30. A method of writing a column of memory cells having a bad memory cell, the method comprising:

producing a segment-in-time (SIT) signal if an address of the column matches a programmed address during a memory access indicating the column has a bad cell;

transmitting data from a data register to a plurality of multiplexors;

transmitting the SIT signal to a corresponding multiplexors to cause the corresponding multiplexor to route data intended for the bad cell from the corresponding multiplexor to a redundant cell.