Radar/IFF simulator circuit for desktop computer

• US 6,301,552 B1
• Filed: 10/27/1998
• Issued: 10/09/2001
• Est. Priority Date: 10/27/1998
• Status: Expired due to Fees

• Current Assignee: Government of The United States of America As Represented By The Secretary of The Navy US Naval Research Laboratory
• Original Assignee: the united states of america as represented by the secretary of the navy
• Inventors: Wilcox, Dwight R., Gomez, Aldan D., Schmiedeberg, David B., Pham, Peter N., Dahlke, Weldon J.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US09/181,024
• Time in Patent Office: 1,078 Days
• Field of Search: 703/13, 703/17, 703/4, 703/2, 342/169, 342/170, 342/171, 342/168, 702/111, 702/106
• US Class Current: 703/4
• CPC Class Codes: G01S 7/4052 by simulation of echoes
• CPC Class Codes: G01S 7/4082 using externally generated reference signals, e.g. via remote reflector or transponder

Abstract

A radar target simulator outputs multiple video and timing signals for a selected radar type from a single computer bus card slot. Several targets including cluster targets may be simulated at conveniently selectable signal-to-noise ratios. Multiple radar types may be simulated concurrently using additional bus card slots in a single desktop computer.

Claims

1. In a personal computer (PC) having a receptacle coupled to a data bus, a radar video output simulator apparatus for generating a simulated radar video signal under computer program control, the apparatus comprising:

a digital interface for coupling to the PC data bus to receive addresses, data, and memory input-output (IO) commands;

a video waveform memory coupled to the digital interface for receiving and storing data representing simulated multi radar target return waveforms;

a digital noise generator coupled to the digital interface for generating data representing pseudorandom noise (PRN); and

a lookup table (LUT) function generator coupled to the digital noise generator and to the video waveform memory for producing a digital signal representing a selectable transformation of a combination of the PRN and the radar target return waveform.

2. The apparatus of claim 1 further comprising in the LUT function generator:

a target selector for defining and selecting a beginning range, an ending range, and a target amplitude corresponding to one or more target return waveforms;

a target multiplexer coupled to the target selector for selecting a LUT address corresponding to one of a single target return waveform plus noise and a cluster target return waveform plus noise;

a LUT address counter for defining a LUT address for loading a transform function value into the LUT;

a LUT address multiplexer coupled to the LUT address counter and the target multiplexer for selecting one of the target multiplexer signal and the LUT address counter signal; and

a LUT coupled to the LUT address multiplexer for producing the digital signal representing a selectable transformation of a combination of the PRN and the radar target return waveform.

3. The apparatus of claim 2 further comprising:

a programmable timing generator coupled to the digital interface for generating a plurality of radar display timing signals including a master clock signal, a pre-trigger (P-TRG) signal, an azimuth reference pulse (ARP) signal, an azimuth change pulse (ACP) signal, a Radar Display Distribution System (RADDS) master trigger (TM) signal and a pulse repetition rate (PRF) signal.

4. The apparatus of claim 3 further comprising:

a digital-to-analog converter (DAC) coupled to the LUT function generator for producing an analog radar video signal corresponding to the selectable transformation of a combination of the PRN and the radar target return waveform.

5. The apparatus of claim 4 wherein the PRN has a bivariate Gaussian distribution.

6. The apparatus of claim 5 wherein the PC data bus receptacle comprises a PC expansion slot.

7. The apparatus of claim 6 wherein the apparatus is disposed in a single printed circuit board (PCB) with plug means for insertion into the PC data bus receptacle.

8. The apparatus of claim 7 wherein the PC data bus comprises:

one of an Integrated Systems Architecture (ISA) bus, a Peripheral Component Interconnect (PCI) bus, a Compact PCI bus, and a Versa Module Europa (VME) bus.

9. The apparatus of claim 1 wherein the PC data bus receptacle comprises a PC expansion slot.

10. The apparatus of claim 9 wherein the apparatus is disposed in a single printed circuit board (PCB) with plug means for insertion into the PC data bus receptacle.

11. The apparatus of claim 1 further comprising:

a programmable timing generator coupled to the digital interface for generating a plurality of radar display timing signals including a master clock signal, a pre-trigger (P-TRG) signal, an azimuth reference pulse (ARP) signal, an azimuth change pulse (ACP) signal, a Radar Display Distribution System (RADDS) master trigger (TM) signal and a pulse repetition rate (PRF) signal.

12. The apparatus of claim 11 further comprising:

a digital-to-analog converter (DAC) coupled to the LUT function generator for producing an analog radar video signal corresponding to the selectable transformation of a combination of the PRN and the radar target return waveform.

13. The apparatus of claim 1 further comprising:

a digital-to-analog converter (DAC) coupled to the LUT function generator for producing an analog radar video signal corresponding to the selectable transformation of a combination of the