Method and apparatus for removing timing hazards in a circuit design

• US 6,301,553 B1
• Filed: 11/02/1998
• Issued: 10/09/2001
• Est. Priority Date: 05/31/1996
• Status: Expired due to Term

• Current Assignee: Mentor Graphics Corporation (Siemens AG), Mentor Graphics Limited (Siemens AG)
• Original Assignee: Mentor Graphics Corporation (Siemens AG)
• Inventors: Emirian, Frederic M., Burgun, Luc M.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US09/184,841
• Time in Patent Office: 1,072 Days
• Field of Search: 703/15, 703/23, 703/19, 716/6, 714/724
• US Class Current: 703/15
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

An apparatus is programmed to automatically remove timing hazards from a circuit design. The apparatus identifies certain level sensitive storage circuit elements in the circuit design. The identified level sensitive storage circuit elements are those having timing hazards. The timing hazards arise as a result of potential skews between the reference signal for the circuit design and the synchronization signal controlling each storage circuit element. A skew, introduced by a gated or divided clock, cannot be assured to be within a design tolerance limit. Therefore, the program enables the apparatus to transform the identified level sensitive storage circuit elements into level sensitive storage circuit elements controlled by synchronization signals that do not have potential skews with respect to the reference signal of the circuit design. The transformation, however, is accomplished without altering the functionality of the circuit design. In effect, the apparatus automatically removes some or all of the timing hazards by determining the appropriate transformation for each of the identified level sensitive storage circuit elements.

Claims

1. An apparatus comprising:

an execution unit for executing programs;

a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing,

the program enables the apparatus to identify certain level sensitive storage circuit elements in a circuit design, said certain level sensitive storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of potential timing skews between delays of these synchronization signals with respect to a reference signal of the circuit design, said potential skews not being ensured to be within a design tolerance limit, the synchronization signals being generated by gating combinatorial logic based on at least the reference signal; and

the program further enables the apparatus to automatically transform said certain level sensitive storage circuit elements to be controlled by synchronization signals with potential skews ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused, the program determining the appropriate transformations for each of said certain level sensitive storage circuit elements employing a Boolean function corresponding to the gating combinatorial logic, and determining at least a first and

a second co-factor value of a logical decomposition of the synchronization signal using the corresponding Boolean function.

2. The apparatus as set forth in claim 1, wherein

the apparatus is enabled by the program to automatically transform said certain level sensitive storage circuit elements controlled by the gated synchronization signals to be controlled by either the reference signal, a constant signal or a divided version of the reference signal multiplied by two, in conjunction with a complementary enable control signal, if appropriate.

3. The apparatus as set forth in claim 2, wherein the apparatus is enabled by the program to determine the appropriate transformation for one of said level sensitive storage circuit elements controlled by a gated synchronization signal, using the Boolean function corresponding to the gating combinatorial logic, and factoring into consideration whether the pre-transformation level sensitive storage circuit element has an enable control signal or not.

4. The apparatus as set forth in claim 1, wherein the apparatus is enabled by the program to represent each of the Boolean functions using a canonical representation.

5. The apparatus as set forth in claim 2, wherein the apparatus is also enabled by the program to insert an AND gate into the circuit design to qualify a complementary enable signal, if employed and the pre-transformation level sensitive storage circuit element has an enable control signal.

6. An apparatus comprising:

an execution unit for executing programs;

a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing,

the program enables the apparatus to identify certain level sensitive storage circuit elements in a circuit design, said certain level sensitive storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of potential timing skews between delays of these synchronization signals with respect to a reference signal of the circuit design, said potential skews not being ensured to be within a design tolerance limit, the synchronization signals being generated by divisional combinatorial logic based on at least the reference signal; and

the program further enables the apparatus to automatically transform said certain level sensitive storage circuit elements to be controlled by synchronization signals that have potential skews which are ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused.

7. The apparatus as set forth in claim 6, wherein the apparatus is enabled by the program to provide the divided synchronization signal as a complementary enable control signal.

8. The apparatus as set forth in claim 7, wherein the apparatus is also enabled by the program to insert an AND gate in the circuit design to qualify the divided synchronization signal by an enable signal of the level sensitive storage circuit element.

9. The apparatus as set forth in claim 7, wherein the apparatus is also enabled by the program to provide a multiplexer to select one of an output of the level sensitive storage circuit element and an input of the level sensitive storage circuit element based on the complementary enable control signal.

10. A computer system comprising:

an execution unit for executing programs;

a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing,

the program enables the computer system to identify certain level sensitive storage circuit elements in a circuit design, said certain level sensitive storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of potential timing skews between delays of these synchronization signals with respect to a reference signal of the circuit design, said skews not being ensured to be within a design tolerance limit, the synchronization signals being generated by gating combinatorial logic based on at least the reference signal; and

the program further enables the computer system to automatically transform said certain level sensitive storage circuit elements to be controlled by synchronization signals that have potential skews which are ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused, the program determining the appropriate transformation for each of said certain level sensitive storage circuit elements employing a Boolean function corresponding to the gating combinatorial logic, and determining at least a first and a second co-factor value of a logical decomposition of the synchronization signal using the corresponding Boolean function.

11. The computer system as set forth in claim 10, wherein

the computer system is enabled by the program to automatically transform said certain level sensitive storage circuit elements controlled by the gated synchronization signals to be controlled by either the reference signal, a constant signal or a divided version of the reference signal multiplied by two, in conjunction with a complementary enable control signal, if appropriate.

12. A computer system comprising:

an execution unit for executing programs;

a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing,

the program enables the computer system to identify certain level sensitive storage circuit elements in a circuit design, said certain level sensitive storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of potential timing skews between delays of these synchronization signals with respect to a reference signal of the circuit design, said skews not being ensured to be within a design tolerance limit, the synchronization signals being generated by division combinatorial logic based on at least the reference signal; and

the program further enables the computer system to automatically transform said certain level sensitive storage circuit elements to be controlled by synchronization signals that have potential skews which are ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused.

13. A computer system comprising:

an execution unit for executing programs;

a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing,

the program enables the computer system to identify certain level sensitive storage circuit elements in a circuit design, said certain level sensitive storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of potential timing skews between delays of these synchronization signals with respect to a reference signal of the circuit design, said potential timing skews not being ensured to be within a design tolerance limit, the synchronization signals being generated by either gating or division combinatorial logic based on at least the reference signal; and

the program further enables the computer system to automatically transform said certain level sensitive storage circuit elements to be controlled by synchronization signals that have potential skews which are ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused, the program first transforming the level sensitive storage circuit elements controlled by synchronization signals generated by gating combinatorial logic, then organizing the remaining ones of the level sensitive storage circuit elements controlled by synchronization signals generated by division combinatorial logic into logical levels, and transforming the remaining ones of the level sensitive storage circuit elements recursively, one logical level at a time.

14. A hardware emulation system comprising:

a host system having an execution unit for executing programs, and a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing,

the program enables the host system to map a circuit design onto logic and interconnect elements of the hardware emulation, including identification of certain level sensitive storage circuit elements in the circuit design, said certain level sensitive storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of potential timing skews between delays of said these synchronization signals with respect to a reference signal of the circuit design, said potential timing skews not being ensured to be within a design tolerance limit, the synchronization signals being generated by gating combinatorial logic based on at least the reference signal;

the program further enables the host system to automatically transform said certain level sensitive storage circuit elements to be controlled by synchronization signals that have potential skews which are ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused, the program determining the appropriate transformation for each of said certain level sensitive storage circuit elements employing a Boolean function corresponding to the gating combinatorial logic, and determining at least a first and a second co-factor value of a logical decomposition of the synchronization signal using the corresponding Boolean function; and

said logic and interconnect elements for emulating said circuit design.

15. The hardware emulation system as set forth in claim 14, wherein

the host system is enabled by the program to automatically transform the level sensitive storage circuit elements controlled by the gated synchronization signals to be controlled by either the reference signal, a constant signal or a divided version of the reference signal multiplied by two, in conjunction with a complementary enable control signal, if appropriate.

16. A hardware emulation system comprising:

a host system having an execution unit for executing programs, and a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing,

the program enables the host system to map a circuit design onto logic and interconnect elements of the hardware emulation system, including identification of certain level sensitive storage circuit elements in the circuit design, said certain level sensitive storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of potential timing skews between delays of these synchronization signals with respect to a reference signal of the circuit design, said potential timing skews not being ensured to be within a design tolerance limit, the synchronization signals being generated by division combinatorial logic based on at least the reference signal;

the program further enables the host system to automatically transform said certain level sensitive storage circuit elements to be controlled by synchronization signals that have potential skews which are ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused; and

said logic and interconnect elements for emulating said circuit design.

17. A hardware emulation system comprising:

a host system having an execution unit for executing programs, and a storage unit coupled to said execution unit, and having stored therein a program for execution by said execution unit during operation, wherein when executing,

the program enables the host system to map a circuit design onto logic and interconnect elements of the hardware emulation system, including identification of certain level sensitive storage circuit elements in the circuit design, said certain level sensitive storage circuit elements being controlled by synchronization signals that can cause timing hazards by virtue of potential timing skews between delays of these synchronization signals with respect to a reference signal of the circuit design, said potential skews not being ensured to be within a design tolerance limit, the synchronization signals being generated by either gating or division combinatorial logic based on at least the reference signal;

the program further enables the host system to automatically transform said certain level sensitive storage circuit elements to be controlled by synchronization signals that have potential skews which are ensured to be within the design tolerance limit, without altering functionality of the circuit design, thereby removing the timing hazards that can be caused, the program first transforming the level sensitive storage circuit elements controlled by synchronization signals generated by gating combinatorial logic, then organizing the remaining ones of the level sensitive storage circuit elements controlled by synchronization signals generated by division combinatorial logic into logical levels, and transforming the remaining ones of the level sensitive storage circuit elements recursively, on e logical level at a time; and

said logic and interconnect elements for emulating said circuit design.

18. An automate d method for removing timing hazards from a circuit design;

said method comprising the steps of;

a) identifying level sensitive storage circuit elements controlled by synchronization signals that are generated by gating combinatorial logic based on at least a reference signal of the circuit design;

b) determining Boolean functions corresponding to the gating combinatorial logic, and determining a first and a second cofactor value of a logical decomposition of each of the gated synchronization signals using the corresponding Boolean function; and

c) automatically transforming each of said level sensitive storage circuit elements controlled by the gated synchronization signals to be controlled by either the reference signal, a constant signal or a divided version of the reference signal multiplied by two, in conjunction with a complementary enable control signal, if appropriate, based at least in part on the first and the second co-factor values determined.

19. The method as set forth in claim 18, wherein said step (c) includes factoring into consideration whether a pre-transformation level sensitive storage circuit element has an enable control signal or not.

20. The method as set forth in claim 18, wherein step (b) includes constructing each of the Boolean functions using a reduced order binary decision diagram.

21. The method as set forth in claim 18, wherein step (c) includes inserting an AND gate into the circuit design to qualify the complementary enable signal, if employed and a pre-transformation level sensitive storage circuit element has an enable control signal.

22. An automated method for removing timing hazards from a circuit design, said method comprising the steps of:

(a) identifying a level sensitive storage circuit element controlled by a synchronization signal that is generated by division combinatorial logic based on at least a reference signal of the circuit design;

(b) automatically transforming said level sensitive storage circuit element from being controlled by the divided synchronization signal to be being controlled by a reference signal in conjunction with a complementary enable control signal.

23. The method as set forth in claim 22, wherein step (b) further includes providing the divided synchronization signal as the complementary enable control signal.

24. The method as set forth in claim 23, wherein step (b) further includes inserting an AND gate in the circuit design to qualify the divided synchronization signal by an enable signal of the level sensitive storage circuit element.

25. The method as set forth in claim 22, wherein step (b) further includes providing a multiplexer to select one of an output of the level sensitive storage circuit element and an input of the level sensitive storage circuit element based on the complementary enable control signal.