Programmable fuzzy analog processor

• US 6,301,570 B1
• Filed: 04/26/1996
• Issued: 10/09/2001
• Est. Priority Date: 04/28/1995
• Status: Expired due to Term

• Current Assignee: Co. Ri.M.Me-Consorzio Per La Ricerca, SGS-Thomson Microelectronics, S.R.L. (STMicroelectronics NV)
• Original Assignee: STMicroelectronics SRL (STMicroelectronics NV)
• Inventors: Franchi, Eleonora, Bruno, Dario, Manaresi, Nicolò, Poluzzi, Rinaldo
• Primary Examiner(s): Chaki, Kakali
• Assistant Examiner(s): STARKS, WILBERT L
• Application Number:
  US08/638,371
• Time in Patent Office: 1,992 Days
• Field of Search: 395/3, 395/900, 706/1, 706/9
• US Class Current: 706/1
• CPC Class Codes: G05F 3/24 wherein the transistors are of the field-effect type only G05F3/205, G05F3/26, G05F3/30 take precedence
• CPC Class Codes: G06N 7/043 Analogue or partially analogue implementation

Abstract

The analog processor of this invention is programmable and capable of storing the processing coefficients in analog form. It comprises a storage section having at least one output, plural outputs in most cases, and being adapted to respectively generate programming signals on such outputs; the storage section is input a plurality of supply voltage signals and is operative to produce, in connection with information stored therein, one of the supply voltage signals on each of the outputs, it being understood that one voltage signal may be produced on several such outputs. Advantageously, the processor can also be programmed in a simple manner from circuits of the digital type if switches controlled by storage elements are used in the storage section.

Claims

1. A fuzzy logic analog processor, comprising:

a processing circuit operable to process at least one fuzzy logic rule, the processing circuit having at least one continuous-time analog voltage, a programming input, and at least one continuous output, the programming input for receiving a programming signal that defines a membership function of the fuzzy logic rule;

a storage circuit including storage elements having at least one output and a plurality of continuous analog inputs each receiving one of a plurality of continuous voltage signals, the storage circuit being operable to provide at its output one of the plurality of continuous voltage signals as the programming signal according to information stored in the storage circuit; and

having a shift register; and

wherein the storage elements include flip-flops connected to the shift register.

2. The fuzzy logic analog processor according to claim 1 wherein the storage elements include memory cells.

3. The fuzzy logic analog processor according to claim 1, further comprising a voltage supply circuit coupled to the processing circuit, and that receives a temperature stable reference voltage and generates the plurality of continuous voltage signals.

4. The fuzzy logic analog processor according to claim 3 wherein the voltage supply circuit comprises:

a voltage divider having a plurality of intermediate laps from which the plurality of continuous voltage signals are provided;

a current mirror connected to the voltage divider; and

a comparator having a first input connected to a temperature stable reference voltage and a second input connected to one of the plurality of intermediate taps, and an output connected to the current mirror.

5. The fuzzy logic analog processor according to claim 1, further comprising a voltage supply circuit that receives a temperature stable reference voltage and generates the plurality of voltage signals, and a bias voltage supply circuit configured to combine a temperature-stable voltage associated with a temperature-stable reference voltage and a threshold-dependent voltage to generate the at least one temperature-stable bias voltage signal.

6. An analog processor, in particular of the fuzzy type, having at least one continuous-time analog input and at least one continuous-time analog output, and comprising:

a continuous-time processing section which is connected to said at least one continuous-time analog input and at least one continuous-time analog output, is input at least one continuous-time analog voltage programming signal, and is adapted to process signals of the analog type, the outcome of such processing being at least dependent on said at least one continuous-time analog voltage programming signal; and

a storage section having at least one continuous-time analog output and being adapted to respectively generate said continuous-time analog voltage programming signal on said output, said storage section being input a plurality of supply continuous-time voltage signals and being adapted to produce, in connection with information stored therein, one of said supply continuous-time voltage signals as the continuous-time analog voltage programming signal on said continuous-time analog output of said storage section; and

wherein said storage section comprises at least a plurality of controlled switches and at least a corresponding plurality of flip flops connected to at least one shift register and having outputs respectively connected to said switches, and is adapted to output, in connection with the contents of said storage elements and through said switches, one of said supply continuous-time voltage signals as the continuous-time analog voltage programming signal.

7. The processor according to claim 6, further comprising a voltage supply section which is input a stable reference potential and is adapted to generate said plurality of supply continuous-time voltage signals and a bias voltage supply circuit configured to combine a temperature-stable voltage associated with a temperature-stable reference voltage and a threshold-dependent voltage to generate the at least one temperature-stable bias voltage signal.

8. The processor according to claim 7 wherein said supply section comprises:

a voltage divider having a plurality of intermediate taps from which said plurality of supply voltage signals are provided;

a current mirror effective to bias said divider;

a transistor effective to drive said mirror; and

a comparator having a first signal input coupled to said reference potential, a second signal input coupled to one of said intermediate taps, and an output coupled to the control terminal of said transistor.

9. The processor according to claim 6 wherein the processor is integrated and implemented with transistors of the MOS type and the processor further comprises a biasing section connected to said processing section and adapted to provide bias therefor by means of at least one voltage signal substantially corresponding to the sum of a voltage proportional to the threshold voltage of the MOS transistors and a temperature-stable voltage proportional to a temperature-stable reference potential.

10. The processor according to claim 9 wherein said reference potential is extracted by division from a signal indicating the width of the variation range of the input or output signals, in particular from a supply potential.

11. The processor according to claim 6 wherein said processing section comprises a plurality of rule blocks having outputs which are coupled together and to said at least one output, each rule block comprising:

at least one fuzzyfier circuit respectively coupled to said at least one continuous-time analog input;

an evaluation circuit coupled to an output of said at least one fuzzyfier circuit; and

a defuzzyfier circuit coupled to an output of said evaluation circuit and having its output coupled to the output of the rule block.

12. The processor according to claim 11 wherein said defuzzyfier circuit comprises a transconductance type of operational amplifier having a current output connected to the output of said defuzzyfier circuit, a first signal input receiving a programming voltage signal from said storage section, a second signal input coupled to its output, and a control input coupled to the output of said evaluation circuit.

13. The processor according to claim 11 wherein said evaluation circuit comprises a transistor of the MOS type having its source terminal coupled to either a supply or ground potential reference, its control terminal coupled to said biasing section, and its drain terminal coupled to a summing node, said summing node being coupled to the output of said at least one fuzzyfier circuit, and said node being further coupled to the output of said evaluation circuit via a unidirectional conduction circuit element.

14. The processor according to claim 11 wherein said fuzzyfier circuit comprises two differential transconductor circuits being substantially identical with each other and having mutually complementary current outputs, and each having a first signal input, a second signal input, and at least one control input for controlling the circuit bias current, said first inputs being coupled together and to said at least one input, said second inputs respectively receiving two programming voltage signals from said storage section, said control inputs being coupled together and to said biasing section, and said outputs being coupled together and to the output of said fuzzyfier circuit.

15. A fuzzy logic circuit comprising:

a continuous-time processing circuit having an input structured to accept an analog voltage input, an output structured to deliver an analog voltage output, and a programming signal input structured to receive programming signals, the processing circuit structured to evaluate the analog voltage input in light of the programming signals and produce the analog voltage output; and

a programming signal generator having a set of programming voltage inputs, and having a set of programming signal outputs coupled to the programming signal input of the processing circuit, the programming signal generator including a plurality of switches, each switch coupled to exactly one of the set of programming voltage inputs at a first terminal and exactly one of the set of programming signal outputs at a second terminal and structured to couple or not couple the first terminal to the second terminal depending on a state of the switch.

16. The fuzzy logic circuit of claim 15 wherein the plurality of switches are MOS transistors each including a respective gate terminal.

17. The fuzzy logic circuit of claim 16 further comprising a plurality of storage devices respectively coupled to the gate terminal of the plurality of MOS transistors.

18. The fuzzy logic processor of claim 17 wherein at least some of the plurality of storage devices are flip-flops.

19. The fuzzy logic processor of claim 18 further comprising a shift register coupled to the flip-flops and structured to enable storing of data into the flip-flops.

20. The fuzzy logic processor of claim 17 wherein at least some of the plurality of storage devices are semiconductor memory devices.

21. The fuzzy logic circuit of claim 15 wherein the set of programming inputs are patterned in columns, wherein the set of programming signal outputs are patterned in rows, and wherein exactly one of the plurality of switches in each row is coupled to its respective column.

22. The fuzzy logic circuit of claim 15 further comprising:

a voltage divider including;

an input voltage terminal structured to accept a temperature-stable voltage reference;

a plurality of resistors coupled as a resistor ladder in series from a first supply voltage to a reference voltage; and

a plurality of resistor taps coupled respectively between the plurality of resistors and the set of programming voltage inputs of the programming signal generator.

23. A fuzzy logic circuit comprising:

a continuous-time processing circuit having an analog voltage input, an analog voltage output, and a programming signal input structured to receive membership functions, the processing circuit structured to operate on signals received at the analog voltage input based on the membership functions and produce a fuzzy logic signal at the analog voltage output; and

a membership function program generator coupled to the processing circuit, the membership function program generator having a set of temperature stable voltage inputs arranged in column form, and having a set of membership function program outputs arranged in row form, the membership function program generator including a plurality of switches, each switch coupled between one of the temperature stable voltage inputs and one of the membership function outputs and each switch structured to selectively couple the one of the temperature stable voltage inputs to the one of the membership function program outputs responsive to a state of the switch.

24. The fuzzy logic circuit of claim 23 wherein the plurality of switches are MOS transistors each including a respective gate terminal.

25. The fuzzy logic circuit of claim 23 further comprising a plurality of storage devices respectively coupled to the gate terminal of the plurality of MOS transistors.

26. The fuzzy logic processor of claim 25 wherein at least some of the plurality of storage devices are data flip-flops.

27. The fuzzy logic processor of claim 26 further comprising a shift register coupled to the flip-flops, the shift register structured to enable storing of data into the data flip-flops.

28. The fuzzy logic processor of claim 25 wherein at least some of the plurality of storage devices are semiconductor memory devices.

29. A MOS fuzzy logic processor comprising:

an analog processing circuit having a set of analog inputs and structured to generate an analog output based on a comparison of input signals received at the set of analog inputs with membership functions generated by a membership function circuit that establishes the membership functions based on a set of analog voltages received at a set of programming inputs; and

a programming section, separate from the processing circuit and including

a plurality of generated analog voltages at a respective plurality of voltage terminals,

a plurality of programming voltage outputs coupled to the set of programming inputs of the analog processing circuit, and

a plurality of coupling devices, each device structured to couple one of the plurality of generated analog voltages to one of the plurality of programming voltage outputs, when activated.

30. The fuzzy logic processor of claim 29 wherein the plurality of generated analog voltages are a set of static analog voltages, each of the static analog voltages available at a respective one of the voltage terminals.

31. The fuzzy logic processor of claim 30 wherein the set of static analog voltages include k voltages having voltage values between a ground voltage and a supply voltage.

32. The fuzzy logic processor of claim 31 wherein the k voltages are equally spaced between the ground voltage and the supply voltage.

33. The fuzzy logic processor of claim 29 wherein the plurality of generated analog voltages are thermally stable with respect to the input signals received at the set of analog inputs of the analog processing circuit.

34. The fuzzy logic processor of claim 29 wherein the coupling devices are fabricated contact structures.

35. The fuzzy logic processor of claim 29 wherein the coupling devices are memory devices.

36. The fuzzy logic processor of claim 35, wherein the memory devices are programmable.

37. The fuzzy logic processor of claim 29, wherein the coupling devices comprise latch circuits coupled to switching devices.

38. A MOS fuzzy logic processor comprising:

an analog processing circuit having a set of analog inputs and structured to generate an output based on a comparison of the set of analog inputs with a membership function circuit that establishes a set of membership functions based on analog voltages received at a set of programming inputs; and

a programming section, separate from the processing circuit and including

a plurality of generated analog voltages,

a plurality of programming voltage outputs coupled to the set of programming inputs of the analog processing circuit, and

means for selectively coupling one of the plurality of generated analog voltages to one of the plurality of programming voltage outputs.

39. The fuzzy logic processor of claim 38 wherein the means for selectively coupling one of the plurality of generated analog voltages to one of the plurality of programming voltage outputs is responsive to an electrical signal.

40. The fuzzy logic processor of claim 38 wherein the means for selectively coupling one of the plurality of generated analog voltages to one of the plurality of programming voltage outputs is programmable.

41. The fuzzy logic processor of claim 38 wherein the plurality of generated analog voltages are a set of static analog voltages, each of the static analog voltages available at a respective circuit node in the programming section of the fuzzy logic processor.

42. A method of programming a fuzzy logic processor that has an analog input, the method comprising:

generating a plurality of continuous static analog voltage signals at a corresponding plurality of voltage contacts within a programming section of the fuzzy logic processor;

selecting a particular one of the plurality of continuous static analog voltage signals to be a programming signal for a particular membership function;

coupling the particular one of the plurality of continuous static analog voltage signals to a programming terminal in the programming section; and

coupling the programming terminal of the programming section to a membership function generating circuit in a processing section of the fuzzy logic processor.

43. The method of claim 42, further comprising:

accepting the analog input at a set of input terminals in the processing section of the fuzzy logic processor;

coupling the analog input to the particular membership function;

comparing the analog input with the membership function; and

generating an analog output of the fuzzy logic processor based on the comparison of the analog input with the membership function.

44. The method of claim 42, further comprising:

repeatedly

selecting a particular one of the plurality of continuous static analog voltage signals to be a particular programming signal for a particular membership function;

coupling the selected static analog voltage signals to programming terminals in the programming section in a one-to-one relationship; and

coupling the programming terminal of the programming section to membership function generating circuits in the processing section of the fuzzy logic processor;

until a selected number of the membership function generating circuits in the processing section of the fuzzy logic processor are coupled to at least one of the plurality of continuous static analog voltage signals.