High speed/low speed interface with prediction cache

• US 6,301,629 B1
• Filed: 03/03/1998
• Issued: 10/09/2001
• Est. Priority Date: 03/03/1998
• Status: Expired due to Term

• Current Assignee: Shared Memory Graphics LLC (Acacia Research Corporation)
• Original Assignee: Alliance Semiconductor Corporation
• Inventors: Alexander, Thomas, Sastri, Bharat, Reddy, Chitranjan N.
• Primary Examiner(s): Nguyen, Hiep T.
• Application Number:
  US09/034,537
• Time in Patent Office: 1,316 Days
• Field of Search: 710/127, 710/128, 710/129, 710/60, 711/118, 711/137, 711/117
• US Class Current: 710/305
• CPC Class Codes: G06F 13/4059 where the synchronisation uses buffers, e.g. for speed matching between buses

Abstract

The present invention provides a monolithic or discrete high speed/low speed interface that is capable of interfacing with the high speed subsystems of a data processing system and low speed subsystems of a data processing system. In one embodiment, the high speed/low speed interface subsystem of the present invention comprises a high speed interface for interfacing with high speed subsystems via a high speed bus, a low speed interface for interfacing with low speed subsystems via a low speed bus, a control circuitry coupled to both the high speed and low speed interfaces, and an internal bus coupled to the control circuitry and the high speed and low speed interfaces. The control circuitry controls the transfer of information between the interfaces. In a second embodiment of the present invention, the high speed/low speed interface subsystem of the present invention comprises all the elements of the first embodiment and a prediction unit. In a third embodiment of the present invention, the high speed/low speed interface subsystem comprises all the elements of the second embodiment and a memory controller. The embodiments of the present invention could be implemented with discrete components or could be implemented on a single semiconductor substrate.

Claims

1. A high speed/low speed data processing system comprising:

a processing unit that includes a high speed interface;

a memory controller that includes a plurality of high speed interfaces;

a first high speed bus, having a first data bandwidth, connected between the high speed interface of the processing unit and a first of the high speed interfaces of the memory controller for transfer of information between the processing unit and the memory controller at an information transfer rate;

a high speed subsystem that includes a high speed interface;

a second high speed bus, having the first data bandwidth, connected between the high speed interface of the high speed subsystem and a second high speed interface of the memory controller for transfer of the information between the high speed subsystem and the memory controller at the information transfer rate;

a high speed/low speed interface system that includes a high speed interface and a low speed interface;

a third high speed bus, having the first data bandwidth, connected between the high speed interface system and a third high speed interface of the memory controller for transfer of information between the high speed/low speed interface system and the memory controller at the information transfer rate.

a low speed subsystem that includes a low speed interface; and

a low speed bus connected between the low speed interface of the low speed subsystem and the low speed interface of the high speed/low speed interface system for transfer of information between the low speed subsystem and the high speed/low speed interface system, the low speed bus having a second bandwidth that is greater than the first bandwidth such that information is transferred between the low speed subsystem and the high speed/low speed interface system at the information transfer rate.

2. The high speed/low speed data processing system as in claim 1, and wherein the high speed interface of the high speed/low speed interface system includes a first-in-first-out (FIFO) memory having its output connected to receive information from the third high speed, and

wherein the low speed interface of the high speed/low speed interface system includes a second FIFO memory having its input connected to the low speed bus, and

wherein the high speed/low speed interface system further includes and intense bus connected to transfer information between the first and second FiFO memories and control circuitry connected to the high speed interface and the lower speed interface as the high speed/low speed interface system to provide control signals thereto for controlling transfer of the information between the first and second FIFO memories via the internal bus.

3. The high speed/low speed data processing system as in claim 2, and wherein the high speed/low speed interfaced system further comprises a prediction unit connected to provide prediction signals to the control circuitry for predicting information to be assessed in the low speed system.

4. The high speed/low speed data processing system as in claim 3, and wherein the prediction unit comprises prediction circuitry that analyzes the history of access requests made by the processing unit for access to the low speed subsystem and that uses the history to predict the next access request to be made by the processing unit for access to the low speed subsystem.