Error propagation path extraction system, error propagation path extraction method, and recording medium recording error propagation path extraction control program

• US 6,301,685 B1
• Filed: 11/19/1998
• Issued: 10/09/2001
• Est. Priority Date: 11/19/1997
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: NEC Corporation
• Inventors: Shigeta, Kazuki
• Primary Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US09/195,548
• Time in Patent Office: 1,055 Days
• Field of Search: 714/3, 714/4, 714/30, 714/45, 714/801, 714/25, 714/799, 714/819, 714/824
• US Class Current: 714/799
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/318371 Methodologies therefor, e.g. algorithms, procedures

Abstract

To realize high-speed error propagation path extraction in a combinational circuit, a logical contradiction judgment section detects the logical state of each signal line under the implication by a first implication section and judges whether the logical state of every signal line is estimated as “0,” “1,” or “X” unless a contradiction is detected. When it is judged that logical state estimation is not completed, a U(Unknown)-state retrieval section retrieves an Unknown-state signal line whose logical state is incomplete and retrieves a signal line connected to an error propagation path through a gate. A detected signal line is decided as “0,” a decision level showing a decision frequency is increased by 1, and implication is restarted by a first implication section. It is judged that logical state estimation is completed, a failing output terminal connection related line extraction section extracts an error propagation path directly influencing a failing output terminal and outputs the route to an output unit.

Claims

1. An error propagation path extraction system for extracting an error propagation path through an inverse logical inference system for estimating the logical state of the input terminal of a combinational circuit in accordance with the logical state of the output terminal of the circuit by using a back track system for estimating the logical state of every signal line by repeating the implication for estimating the logical state of the input/output line of a gate not estimated yet in accordance with the logical state of the input/output line of a gate already estimated;

the system comprising;

error propagation path influenced line retrieval means for retrieving a signal line connected with said error propagation path as said signal line whose logical state is an object to be decided; and

failing output terminal connection related line extraction means for extracting a signal line having a possibility of propagating an error to a failing output terminal from said error propagation path in accordance with the retrieval result by said error propagation path influenced line retrieval means.

2. The error propagation path extraction system according to claim 1, wherein said error propagation path influenced line retrieval means is constituted so as to retrieve a signal line connected with said error propagation path when retrieving a signal line whose logical state is indeterminate and which is an object to be decided.

3. The error propagation path extraction system according to claim 1, wherein said failing output terminal connection related line extraction means is constituted so as to extract a signal line having a possibility of propagating an error to a failing output terminal by checking the physical relation between an extracted error propagation path and a failing output terminal in accordance with the route.

4. The error propagation path extraction system according to claim 1, wherein implication means for executing said implication while confirming whether a contradiction occurs between the logical state estimated through said implication and the logical state estimated by that point of time.

5. An error propagation path extraction method for extracting an error propagation path through an inverse logical inference system for estimating the logical state of the input terminal of a combinational circuit in accordance with the logical state of the output terminal of the circuit by using the back track system for estimating the logical state of every signal line by repeating the implication for estimating the logical state of the input/output line of a gate not estimated yet in accordance with the logical state of the input/output line of a gate already estimated, the method comprising the steps of:

retrieving a signal line connected with said error propagation path as said signal line whose logical state is an object to be decided; and

extracting a signal line having a possibility of propagating an error to a failing output terminal from said error propagation path in accordance with the retrieval result by said error propagation path influenced line retrieval means.

6. The error propagation path extraction method according to claim 5, wherein the step of retrieving a signal line connected with said error propagation path retrieves a signal line connected with said error propagation path when retrieving a signal line whose logical state is indeterminate and which is an object to be decided.

7. The error propagation path extraction method according to claim 5, wherein the step of extracting a signal line having a possibility of propagating an error to a failing output terminal from said error propagation path extracts a signal line having a possibility of propagating an error to said failing output terminal by checking the physical connective relation between an extracted fault output route and said failing output terminal in accordance with the route.

8. The error propagation path extraction method according to claim 5, wherein the step of executing said implication while confirming whether a contradiction occurs between the logical state estimated through said implication and the logical state estimated by that point of time is included.

9. A recording medium adapted to record an error propagation path extraction control program for extracting an error propagation path with the inverse logical inference system for estimating the logical state of the input terminal of a combinational circuit in accordance with the logical state of the output terminal of the circuit by using a back track system for estimating the logical state of every signal line by repeating the implication for estimating the logical state of the input/output line of a gate not estimated yet in accordance with the logical state of the input/output line of a gate already estimated and the logical state decision, wherein said error propagation path extraction control program makes control means for controlling extraction of said error propagation path retrieve a signal line connected with said error propagation path as said signal line whose logical state is an object to be decided and extract a signal line having a possibility of propagating an error to a failing output terminal from said error propagation path in accordance with the retrieval result by an error propagation path influence line retrieval means.

10. The recording medium adapted to record an error propagation path extraction control program according to claim 9, wherein said error propagation path extraction control program makes said control means retrieve a signal line connected with said error propagation path when retrieving a signal line whose logical state is indeterminate and which is an object to be decided.

11. The recording medium adapted to record an error propagation path extraction control program according to claim 9, wherein said error propagation path extraction control program makes said control means extract a signal line having a possibility of propagating an error to a failing output terminal by checking the physical connective relation between an extracted fault output route and said failing output terminal in accordance with the route.

12. The recording medium adapted to record an error propagation path extraction control program according to claim 9, wherein said error propagation path extraction control program makes said control means execute said implication while confirming whether a contradiction occurs between the logical state estimated through said implication and the logical state estimated by the point of time.