Spacing violation checker

• US 6,301,689 B1
• Filed: 09/28/1998
• Issued: 10/09/2001
• Est. Priority Date: 09/28/1998
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Darden, Laura R.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): THOMPSON, ANNETTE M
• Application Number:
  US09/162,215
• Time in Patent Office: 1,107 Days
• Field of Search: 716/5
• US Class Current: 716/112
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A spacing violation checker that forms conductor rectangles, forms minimum spacing rectangles, identifies possible errors and checks whether possible errors are true errors allows same net spacing errors to be recognized during physical design prior to the design rules check. The software supporting the invention performs orders of magnitude faster than the design rules check solution. As such, the invention dramatically decreases the turn-around time of physical design, providing a fast solution which is available prior to final layout release.

Claims

1. A process of testing spacing of wiring in a circuit comprising:

forming a plurality of conductor rectangles representative of conductors of said circuit;

forming minimum spacing rectangles around said conductor rectangles, said minimum spacing rectangles being larger than respective ones of said conductor rectangles;

identifying a possible error rectangle when a first conductor rectangle of said conductor rectangles occupies a portion of a minimum spacing rectangle of a second conductor rectangle of said conductor rectangles;

checking whether said possible error rectangle is a true error; and

reporting said true errors;

wherein said checking comprises;

classifying said possible error rectangle as a possible diagonal error rectangle or a possible non-diagonal error rectangle;

determining that said possible diagonal error rectangle is said not a true error when at least two adjacent sides of said possible diagonal error rectangle which intersect said first conductor and said second conductor are covered by a third conductor of said conductors; and

determining that said possible non-diagonal error rectangle is not a true error when said possible non-diagonal error rectangle is completely covered by said third conductor.

2. A process of testing spacing of elements in a structure comprising:

forming a plurality of element rectangles representative of elements of said structure;

forming minimum spacing rectangles around said element rectangles, said minimum spacing rectangles being larger than respective ones of said clement rectangles;

identifying a possible error rectangle when a first element rectangle of said element rectangles occupies a portion of a minimum spacing rectangle of a second element rectangle of said element rectangles;

checking whether said possible error rectangle is a true error; and

reporting said true errors;

wherein said checking comprises;

classifying said possible error rectangle as a possible diagonal error rectangle or a possible non-diagonal error rectangle;

determining that said possible diagonal error rectangle is said not a true error when at least two adjacent sides of said possible diagonal error rectangle which intersect said first element and said second element are covered by a third element of said elements; and

determining that said possible non-diagonal error rectangle is not a true error when said possible non-diagonal error rectangle is completely covered by said third element.

3. A computer system for testing spacing of wiring in a circuit comprising:

a unit for forming a plurality of conductor rectangles representative of conductors of said circuit;

a unit for forming minimum spacing rectangles around said conductor rectangles, said minimum spacing rectangles being larger than respective ones of said conductor rectangles;

a unit for identifying a possible error rectangle when a first conductor rectangle of said conductor rectangles occupies a portion of a minimum spacing rectangle of a second conductor rectangle of said conductor rectangles;

a unit for checking whether said possible error rectangle is a true error; and

a unit for reporting said true errors;

wherein said unit for checking comprises;

a unit for classifying said possible error rectangle as a possible diagonal error rectangle or a possible non-diagonal error rectangle;

a unit for determining that said possible diagonal error rectangle is said not a true error when at least two adjacent sides of said possible diagonal error rectangle which intersect said first conductor and said second conductor are covered by a third conductor of said conductors; and

a unit for determining that said possible non-diagonal error rectangle is not a true error when said possible non-diagonal error rectangle is completely covered by said third conductor.

4. A computer program product comprising a program storage device readable by a computer system tangibly embodying a program of instructions executed by said computer system to perform a process for testing spacing of wiring in a circuit, said process comprising:

forming a plurality of conductor rectangles representative of conductors of said circuit;

forming minimum spacing rectangles around said conductor rectangles, said minimum spacing rectangles being larger than respective ones of said conductor rectangles;

identifying a possible error rectangle when a first conductor rectangle of said conductor rectangles occupies a portion of a minimum spacing rectangle of a second conductor rectangle of said conductor rectangles;

checking whether said possible error rectangle is a true error; and

reporting said true errors;

wherein said checking comprises;

classifying said possible error rectangle as a possible diagonal error rectangle or a possible non-diagonal error rectangle;

determining that said possible diagonal error rectangle is said not a true error when at least two adjacent sides of said possible diagonal error rectangle which intersect said first conductor and said second conductor are covered by a third conductor of said conductors; and

determining that said possible non-diagonal error rectangle is not a true error when said possible non-diagonal error rectangle is completely covered by said third conductor.