Methods to securely configure an FPGA using macro markers

• US 6,301,695 B1
• Filed: 01/14/1999
• Issued: 10/09/2001
• Est. Priority Date: 01/14/1999
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Lawman, Gary R., Burnham, James L.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Kik, Phallaka
• Application Number:
  US09/231,912
• Time in Patent Office: 999 Days
• Field of Search: 716/1-21, 713/1, 713/2, 713/100, 340/825-3-8
• US Class Current: 716/117
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

A method is provided for securely configuring an FPGA with macros. Specifically, if an end user desires to use a macro from a macro vendor, the end user creates a marked design file containing a macro marker rather than the actual macro. The marked design file is converted into configuration data by a macro manager. Specifically, the macro manager obtains the macro from the macro vendor and replaces the macro marker with the macro prior to converting the design file into configuration data. The macro manager provides the configuration data to the end user. Because only the macro manager has access to the macro, the possibility of unlicensed use of the macro is diminished.

Claims

1. A method to program an FPGA comprising the steps of:

creating a marked design file incorporating a first macro marker identifying a first macro and further incorporating a user design including said first macro;

replacing said first macro marker with said first macro in said marked design file; and

converting said marked design file into configuration data, wherein said configuration data incorporates said first macro and said user design.

2. The method of claim 1, further comprising the step of obtaining said first macro marker from a first macro vendor.

3. The method of claim 1, further comprising the step of obtaining said first macro from a first macro vendor.

4. The method of claim 3, wherein said step of obtaining said first macro from a first macro vendor is performed by a macro manager.

5. The method of claim 1, further comprising the step of programming said FPGA with said configuration data.

6. The method of claim 5, wherein said step of programming said FPGA with said configuration data is performed by an end user.

7. The method of claim 5, wherein said step of converting said marked design file into configuration data is performed by a macro manager.

8. The method of claim 1, wherein said step of creating a marked design file incorporating a first macro marker identifying a first macro is performed by an end user.

9. The method of claim 1, further comprising the step of incorporating a second macro marker identifying a second macro in said marked design file.

10. The method of claim 9, wherein said configuration data incorporates said second macro.

11. The method of claim 9, further comprising the step of obtaining said second macro marker from a second macro vendor.

12. The method of claim 11, wherein said step of obtaining said second macro marker from a second macro vendor is performed by an end user.

13. The method of claim 9, further comprising the step of obtaining said second macro from a second macro vendor.

14. The method of claim 13, wherein said step of obtaining said second macro from a second macro vendor is performed by a macro manager.

15. A method to program an FPGA comprising the steps of:

creating a marked design file incorporating a first macro marker identifying a first macro;

providing said marked design file to a macro manager, wherein said macro manager incorporates said first macro into said marked design file based on said first macro marker; and

receiving configuration data from said macro manager based on said marked design file.

16. The method of claim 15, further comprising the step of obtaining said first macro marker from a first macro vendor.

17. The method of claim 15, further comprising the step of programming said FPGA with said configuration data.

18. The method of claim 15, further comprising the step of incorporating a second macro marker identifying a second macro in said marked design file.

19. The method of claim 15, wherein said marked design file is provided to said macro manager by way of a secured medium.

20. The method of claim 19, wherein said secured medium is an encrypted channel of a public network.

21. A method to acquire a programmed FPGA, the method comprising the steps of:

creating a marked design file incorporating a first macro marker identifying a first macro;

providing said marked design file to a macro manager, wherein the macro manager incorporates said first macro into said marked design file based on said first macro marker, generates configuration data based on said marked design file, and programs an FPGA with said configuration data to generate the programmed FPGA; and

receiving the programmed FGPA from the macro manager.

22. The method of claim 21, further comprising the step of obtaining said first macro marker from a first macro vendor.

23. The method of claim 21, further comprising the step of incorporating a second macro marker identifying a second macro in said marked design file.

24. A method to program an FPGA comprising the steps of:

receiving a marked design file incorporating a first macro marker identifying a first macro from an end user;

replacing said first macro marker with said first macro in said marked design file; and

converting said marked design file into configuration data.

25. The method of claim 24, further comprising the step of providing said configuration data to said end user.

26. The method of claim 24, further comprising the steps of:

programming said FPGA with said configuration data; and

providing said FPGA to said end user.

27. The method of claim 24, wherein said marked design file incorporates a second macro marker identifying a second macro.

28. The method of claim 24, further comprising the step of obtaining said first macro from a first macro vendor.

29. The method of claim 24, where said step of converting said marked design file into configuration data comprises a step of replacing said first macro marker with said first macro.