Methods of forming power semiconductor devices having T-shaped gate electrodes

• US 6,303,410 B1
• Filed: 04/12/2000
• Issued: 10/16/2001
• Est. Priority Date: 06/01/1998
• Status: Expired due to Term

• Current Assignee: Hanger Solutions, LLC (IP Investments Group LLC)
• Original Assignee: North Carolina State University (University of North Carolina System)
• Inventors: Baliga, Bantval Jayant
• Primary Examiner(s): Pham, Long
• Application Number:
  US09/547,544
• Time in Patent Office: 552 Days
• Field of Search: 438/133, 438/135, 438/138, 438/136, 438/137, 438/542, 438/546, 438/547, 438/556
• US Class Current: 438/138
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

Power semiconductor devices having recessed gate electrodes are formed by methods which include the steps of forming a semiconductor substrate having a drift region of first conductivity type therein extending to a face thereof and forming a trench in the substrate so that the trench has a bottom which extends opposite the drift region and a sidewall which extends from the drift region to the face. The sidewall may extend orthogonal to the face or at an angle greater than 90°. A preferred insulated gate electrode is formed by lining the face and trench with a gate electrode insulating layer and then forming a conductive layer on the gate electrode insulating layer. The conductive layer is preferably formed to extend opposite a portion of the face adjacent to the trench and into the trench. A step is then performed to pattern the conductive layer to define a T-shaped or Y-shaped gate electrode which fills the trench and also extends opposite the face at a location adjacent the trench. This step is preferably performed without planarizing the conductive layer using techniques such as chemical mechanical polishing (CMP). Emitter/source and base regions of first and second conductivity type, respectively, are then formed in the drift region. Preferably, the emitter/source regions are formed in a self-aligned manner to an edge of the patterned gate electrode. In particular, the emitter/source region and base region may be formed by implanting emitter/source and base region dopants into the drift region, using the gate electrode as an implant mask, and then diffusing the implanted dopants to define an emitter/source region within a base region well.

Claims

1. A method of forming a semiconductor switching device, comprising the steps of:

forming a semiconductor substrate having a drift region of first conductivity type therein extending adjacent a face thereof;

forming a trench in the substrate, said trench having a bottom that extends adjacent the drift region and a sidewall that extends to the face;

forming a gate electrode insulating layer in the trench;

forming a conductive layer on the substrate, said conductive layer extending opposite a first portion of the face that intersects the sidewall of the trench and onto the gate electrode insulating layer in the trench;

patterning the conductive layer to define a T-shaped gate electrode that fills the trench and also extends opposite the first portion of the face; and

forming emitter and base regions of first and second conductivity type, respectively, that are self-aligned to the T-shaped gate electrode and extend in the drift region, by;

implanting emitter and base region dopants into the face using the T-shaped gate electrode as an implant mask; and

then

simultaneously laterally diffusing the implanted emitter and base region dopants into the drift region for a sufficient duration so that the base region extends to and along the first portion of the face and also extends to and along an upper portion of the sidewall of the trench and the source region extends underneath an edge of the T-shaped gate electrode but does not extend to an intersection between the sidewall of the trench and the first portion of the face.

2. The method of claim 1, wherein said step of forming emitter and base regions comprises implanting emitter and base region dopants into the drift region, using the gate electrode as an implant mask.

3. The method of claim 2, wherein said step of patterning the conductive layer is not preceded by a step of planarizing the conductive layer.

4. The method of claim 2, wherein said step of implanting emitter and base region dopants is not preceded by a step of planarizing the conductive layer.

5. The method of claim 1, wherein said step of forming a gate electrode insulating layer comprises forming a gate electrode insulating layer on the face and on the sidewall and bottom of the trench;

and wherein said step of forming emitter and base regions is not preceded by a step of planarizing the conductive layer or a step of planarizing the gate electrode insulating layer.

9. The method of claim 1, wherein said step of simultaneously laterally diffusing the implanted emitter and base region dopants is of sufficiently short duration that a maximum depth to which the base region extends along the upper portion of the sidewall of the trench is less than a maximum depth of the base region relative to the face.

11. The method of claim 1, wherein all portions of the T-shaped gate electrode have a T-shaped transverse cross-section.

6. A method of forming a semiconductor switching device, comprising the steps of:

forming a semiconductor substrate having a drift region of first conductivity type therein extending adjacent a face thereof;

forming a trench in the drift region;

then

forming a T-shaped insulated gate electrode in the trench and on a first portion of the face extending adjacent the trench; and

then

forming emitter and base regions of first and second conductivity type, respectively, that extend into the drift region and are self-aligned to the T-shaped insulated gate electrode, by;

implanting emitter and base region dopants into the face using the T-shaped insulated gate electrode as an implant mask; and

then

simultaneously laterally diffusing the implanted emitter and base region dopants into the drift region for a sufficient duration so that the base region extends to and along the first portion of the face and also extends to and along an upper portion of a sidewall of the trench and the source region extends underneath an edge of the T-shaped gate electrode but does not extend to an intersection between the sidewall of the trench and the first portion of the face.

7. The method of claim 6, wherein said step of forming a T-shaped insulated gate electrode comprises:

forming a gate electrode insulating layer on the face and in the trench;

forming an electrically conductive layer on the gate electrode insulating layer so that the electrically conductive layer extends opposite a portion of the face adjacent to the trench and fills the trench; and

etching the electrically conductive layer and gate electrode insulating layer to expose the face.

8. The method of claim 7, wherein said step of forming emitter and base regions is not preceded by a step of planarizing the electrically conductive layer.

10. The method of claim 6, wherein said step of simultaneously laterally diffusing the implanted emitter and base region dopants is of sufficiently short duration that a maximum depth to which the base region extends along the upper portion of the sidewall of the trench is less than a maximum depth of the base region relative to the face.

12. The method of claim 6, wherein all portions of the T-shaped insulated gate electrode have a T-shaped transverse cross-section.