Method of forming PID protection diode for SOI wafer

• US 6,303,414 B1
• Filed: 07/12/2000
• Issued: 10/16/2001
• Est. Priority Date: 07/12/2000
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Quek, Shyue Fong, Ang, Ting Cheong, Song, Jun, Loong, Sang Yee
• Primary Examiner(s): Le, Vu A.
• Assistant Examiner(s): SMITH, BRADLEY
• Application Number:
  US09/614,558
• Time in Patent Office: 461 Days
• Field of Search: 438/155, 438/151, 438/149, 438/142, 257/355
• US Class Current: 438/155
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688

Abstract

An integrated microelectronics semiconductor circuit fabricated on a silicon-on-insulator (SOI) type substrate can be protected from unwanted current surges and excessive heat buildup during fabrication by means of a heat-dissipating, protective plasma-induced-damage (PID) diode. The present invention fabricates such a protective diode as a part of the overall scheme in which the transistor devices are formed.

Claims

1. A method of forming a heat-dissipating PID protective diode for an integrated semiconductor microelectronics circuit on an SOI substrate, comprising:

providing an SOI substrate;

forming and patterning a first photoresist layer on said SOI substrate;

forming a plurality of shallow trench isolation (STI) regions through said photoresist layer by means of a first etch process and STI oxide deposition, then removing said photoresist layer and planarizing the substrate;

forming and patterning a second photoresist layer on said SOI substrate;

removing a portion of STI and SOI oxide layer and exposing the lower silicon layer by a second etch process through said second photoresist layer and then removing said photoresist layer;

forming and patterning a third photoresist layer on said SOI substrate and implanting a certain low density of dopant ions into the exposed portion of the lower silicon layer through said third photoresist layer, forming thereby a PID protective np-diode structure and then removing said photoresist layer;

patterning and etching a plurality of gate electrodes and sidewall spacers over selected portions of the upper silicon layer of the SOI substrate, forming thereby a portion of a microelectronics fabrication in the upper silicon layer;

forming and patterning a fourth photoresist layer on said SOI substrate and implanting a certain high density of dopant ions through said photoresist layer into the exposed low density doped region of the PID protective diode in the lower silicon layer, forming thereby a region of higher dopant density and improved conductive contact properties within the region of lower dopant density and also implanting said high density of dopant ions into selected regions of the upper silicon layer to form, thereby, source and drain regions for a plurality of transistors in the microelectronics fabrication and then removing said photoresist layer;

implanting a certain high density of dopant ions into selected regions of the upper silicon layer of the SOI substrate to form, thereby, silicided implanted source and drain regions for a plurality of transistors;

forming silicide contacts on the source, drain and gate regions of the transistors by a salicide process;

forming an interlayer dielectric (ILD) over the fabrication;

forming conducting contacts to the silicided regions of selected transistors of the microelectronics fabrication or to other selected circuit elements and to the implanted high dopant density region of the PID protective diode formed in the lower silicon layer of the SOI substrate, completing, thereby, a PID protective diode structure for the entire fabrication;

forming a metal layer over the ILD layer, said metal layer being in electrical contact with the contact from the PID diode, but not being in electrical contact with the contacts of the selected transistors or circuit elements;

forming, if required, additional levels of microelectronic integration over the fabrication;

forming, over each such additional level, a metal layer connected, through vias, to the PID protective diode.

2. The method of claim 1 wherein the SOI substrate is formed by the SIMOX method or by a method of wafer bonding.

3. The method of claim 1, wherein the upper and lower silicon layers of the SOI substrate are doped with a low density of p-type ions.

4. The method of claim 1, wherein the first etch process is an etch by a chemical etchant chosen from among the group consisting of Cl₂, HBr and SF₆.

5. The method of claim 3, wherein the low density of ions implanted through the third photoresist layer are n-type ions such as As or P ions, and they are implanted to a density of between 5E13 and 1E15 ions per cubic centimeter.

6. The method of claim 5, wherein the high density ions implanted through the fourth photoresist layer are n-type ions such as As or P ions and they are implanted to a density of between 1E15 and 5E15 ions per cubic centimeter.

7. The method of claim 1, wherein the high density of ions implanted into selected regions of the upper silicon layer to form source and drain regions are p-type ions, such as B or BF₂ ions and they are implanted to a density of between 5E13 and 1E15 ions per cubic centimeter.

8. The method of claim 1, wherein the ILD is formed of a layer of dielectric material chosen from among the group consisting of BPSG, FSG, USG or various oxides, with a thickness of between 6000 angstroms and 20,000 angstroms.

9. The method of claim 1, wherein the contacts through the ILD to the PID diode and silicided regions of the MOS devices are formed of tungsten.

10. The method of claim 1, wherein the metal layer covering the ILD is shaped such that it optimally collects excess charges and dissipates heat generated by subsequent fabrication processes, such shapes consisting of, but not limited to, perimeter pieces, fingers and antenna shaped projections, formed so as to maintain a certain minimum distance from any nearby conductive contacts to the circuitry below.

11. The method of claim 10, wherein the spacing between the metal layer and any nearby conductive contacts is at least the width of those conductive contacts.