Programmable logic device, information processing system, method of reconfiguring programmable logic device and method compressing circuit information for programmable logic device

• US 6,304,101 B1
• Filed: 06/02/2000
• Issued: 10/16/2001
• Est. Priority Date: 07/14/1999
• Status: Expired due to Term

• Current Assignee: Fuji Xerox Company Limited (Xerox Holdings Corp.)
• Original Assignee: Fuji Xerox Company Limited (Xerox Holdings Corp.)
• Inventors: Nishihara, Yoshio
• Primary Examiner(s): Tokar, Michael
• Assistant Examiner(s): Chang, Daniel D.
• Application Number:
  US09/585,447
• Time in Patent Office: 501 Days
• Field of Search: 326/38, 326/39, 326/40, 326/41, 326/46, 326/47, 711/104, 711/103, 711/170, 716/5, 716/16
• US Class Current: 326/41
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17758 for speeding up configuration or reconfiguration
• CPC Class Codes: H03K 19/1776 for memories

Abstract

The invention is made to implement technique similar to multicontext technique without using a configuration memory for storing plural circuit information pieces that causes deterioration of circuit performance, increase of power consumption, increase of processes and increase of the manufacturing cost. Therefore, in a programmable logic device, a circuit information storage different from the configuration memory and a circuit information editor for generating circuit information of a specified circuit using circuit information stored in the circuit information storage are provided. In the circuit information storage, circuit information of plural circuits is stored in a compressed state. When specification information of the circuit information of a reconfigured circuit is input to a programmable logic circuit, the circuit information editor reads required circuit information from the circuit information storage, decompresses compressed circuit information, generates circuit information specified in the specification information, transfers the generated circuit information to a configuration memory and reconfigures the circuit.

Claims

1. A programmable logic device, comprising:

a programmable logic circuit provided with a circuit element and a configuration memory connected to the circuit element in which a circuit is configured based upon circuit information written to the configuration memory;

a circuit information storage different from the configuration memory that stores plural circuit information pieces for sequentially configuring plural circuits in the programmable logic circuit;

a circuit information writer that writes the plural circuit information pieces to the circuit information storage;

a circuit information editor that generates, in the programmable logic circuit, the circuit information of one, circuit specified in specification information using one or plural circuit information pieces out of the plural circuit information pieces stored in the circuit information storage; and

a controller that writes the circuit information of the circuit generated by the circuit information editor to, the configuration memory.

2. A programmable logic device according to claim 1, wherein:

the circuit information storage and the circuit information editor are provided separately from the programmable logic circuit.

3. A programmable logic device according to claim 1, wherein:

the circuit information editor generates circuit information in part of the circuit element of the programmable logic circuit by writing the circuit information to part of the configuration memory.

4. A programmable logic device according to claim 1, wherein:

the circuit information stored in the circuit information storage is compressed; and

the compressed circuit information is decompressed by the circuit information editor and circuit information specified in-the specification information is generated.

5. A programmable logic device according to claim 1, wherein:

the circuit information stored in the circuit information storage is provided with reference information for reading other circuit information from the circuit information storage in the case where part or all of the circuit information is composed of other circuit information; and

the circuit information editor acquires circuit information of one circuit specified in the specification information from the circuit information storage, and in the case where reference information is included in the circuit information, the circuit information editor generates the circuit information of the specified circuit by acquiring the other circuit information based upon the reference information.

6. A programmable logic device according to claim 1, wherein:

circuit information stored in the circuit information storage is provided with reference information for referring to another part of the circuit information itself in the case where part of the circuit information is composed of another part of the circuit information itself; and

the circuit information editor acquires circuit information of the specified circuit from the circuit information storage, and in the case where reference information is included, the circuit information editor generates the circuit information of a circuit specified in the specification information also using the reference information.

7. A programmable logic device according to claim 1, wherein:

each of the plural circuit information pieces stored in the circuit information storage includes a circuit data division and its additional information division;

the additional information division includes description to instruct the circuit information editor to edit the circuit data division;

the circuit data division in data for configuring a circuit in the programmable logic circuit and in the case where part or all of the division is composed of a circuit data division of other circuit information, the part or all of the circuit data division includes description of reference information for referring to the other circuit information in the circuit information storage; and

the circuit information editor acquires circuit information specified in the specification information and a circuit data division of the other circuit information referred to by the reference information from the circuit information storage to generate the circuit information specified in the specification information.

8. A programmable logic device according to claim 1, wherein:

each of the plural circuit information pieces stored in the circuit-information storage includes a circuit data division and its additional information division;

the additional information division includes description to instruct the circuit information editor to edit the circuit data division;

the circuit data division is data for configuring a circuit in the programmable logic circuit, and in the case where part of the division in composed of another circuit data division of its own circuit information, the part includes description using reference information for referring to another circuit data division; and

the circuit information editor acquires circuit information specified in the specification information from the circuit information storage, and in the case where reference information is included, the circuit information editor generates the circuit information specified in the specification information also using the reference information.

9. A programmable logic device according to claim 7, wherein:

the circuit data division of circuit information stored in the circuit information storage is described in one or plural frames equivalent to data segmented per every fixed quantity in the configuration memory; and

in the case where part or all of the one or plural frames are composed of a frame of other circuit information, the reference information is described as circuit data of a frame to refer to the frame of the other circuit information in the corresponding circuit information.

10. A programmable logic device according to claim 7, wherein;

the circuit data division of circuit information stored in the circuit information storage is described in one or plural frames equivalent to data segmented per every fixed quantity in the configuration memory; and

in the case where part of the one or plural frames is composed of another frame in its own circuit information, the reference information is described as circuit data of a frame to refer to the frame-of its own circuit information in the corresponding circuit information.

11. A programmable logic device according to claim 9, wherein:

in the case where the reference information is described in a frame in the circuit information of a circuit to be generated, the circuit information editor does not transfer data in a frame to the configuration memory via the controller when data in a frame position where reference information is described is determined to be identical to data in a frame in the same position of the circuit information of a circuit generated immediately before in the programmable logic circuit.

12. An information processing system that performs at least a part of processing by an application program in a programmable logic device, wherein:

the programmable logic device according to claim 1 is used as the programmable logic device.

13. A method of reconfiguring a circuit in a programmable logic device, comprising the steps of:

providing a circuit information storage different from a configuration memory, which stores plural circuit information pieces for sequentially configuring plural circuits in the programmable logic circuit and a circuit information editor that generates the-circuit information of a specified circuit using circuit information stored in the circuit information storage to the programmable logic device equipped with a programmable logic circuit having a circuit element and the configuration memory connected to the circuit element where a circuit is configured based upon circuit information written to the configuration memory;

storing circuit information of the plural circuits in the circuit information storage in a compressed state; and

upon input of specification information of the circuit information of a reconfigured circuit to the programmable logic circuit, reading required circuit information by the circuit information editor from the circuit information storage;

decompressing the compressed circuit information to generate circuit information specified in the specification information; and

transferring the generated circuit information to the configuration memory to reconfigure the circuit.

14. A method of reconfiguring a circuit in the programmable logic device according to claim 13, wherein;

circuit information stored in the circuit information storage is compressed by, describing reference information for reading other circuit information from the circuit information storage in the case where part or all of the circuit information is composed of other circuit information; and

the circuit information editor acquires required circuit information from the circuit information storage based upon reference information in the case where the specified circuit information read from the circuit information storage Includes the reference information.

15. A method of reconfiguring a circuit in the programmable logic device according to claim 13, wherein:

circuit information stored in the circuit information storage is compressed by describing reference information for referring to another part of the circuit information Itself in the case where part of the circuit information is composed of another part of the circuit information itself; and

the circuit information editor generates required circuit information using the read circuit information based upon the reference information in the case where the specified circuit information read from the circuit information storage includes the reference information.

16. A method of reconfiguring a circuit in the programmable logic device according to claim 14, wherein:

each of the plural circuit information pieces stored in the circuit information storage includes a circuit data division and its additional information division;

the additional information division includes description to instruct the circuit information editor to edit the circuit data division; and

the circuit data division is compressed using the reference information.

17. A method of reconfiguring a circuit in the programmable logic device according to claim 14, wherein:

the circuit data division is described in one or plural frames equivalent to data segmented per every fixed quantity in the configuration memory; and

in the case where part or all of the one or plural frames are composed of the frame of other circuit information, the reference information is described in the corresponding circuit information as the circuit data of a frame to refer to the frame of the other circuit information.

18. A method of reconfiguring a circuit in the programmable logic device according to claim 14, wherein:

the circuit data division is described in one or plural frames equivalent to data segmented per every fixed quantity in the configuration memory; and

in the case where part of the one or plural frames is composed of another frame in its own circuit information, the reference information is described in the corresponding circuit information as the circuit data of a frame to refer to the frame of its own circuit information.

19. A method of controlling plural circuit information pieces for sequentially configuring plural circuits in a programmable logic device, the method comprising the steps of:

describing each of the circuit information pieces in one or plural frames equivalent to data segmented per every fixed quantity in a configuration memory in the programmable logic device and; and

in the case where part or all of the circuit information is composed of other circuit information or another part in the circuit information itself, describing reference information in the corresponding circuit information as another circuit information or the circuit data of a frame to refer to the frame of its own circuit information.

20. A method of compressing circuit information, comprising the steps of:

describing circuit data division of circuit information for configuring a circuit in a programmable logic device in a set of frames equivalent to data segmented per every fixed quantity in a configuration-memory of a programmable logic circuit; and

in the case where part oral I of the circuit information is composed of other circuit information or another part of the circuit information itself, compressing the data quantity of circuit information by describing reference information in the corresponding circuit information as other circuit information or the circuit data of a frame to refer to the frame of its own circuit information.