Disparity and transition density control system and method

• US 6,304,196 B1
• Filed: 10/19/2000
• Issued: 10/16/2001
• Est. Priority Date: 10/19/2000
• Status: Expired due to Term

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Tezcan, Bertan, Copeland, Greg
• Primary Examiner(s): Williams, Howard L.
• Assistant Examiner(s): Jeanglaude, Jean Bruner
• Application Number:
  US09/692,602
• Time in Patent Office: 362 Days
• Field of Search: 341/58, 341/50, 708/410, 708/400
• US Class Current: 341/58
• CPC Class Codes: H04N 19/60 using transform coding

Abstract

A system and method for encoding and decoding data utilizes Walsh-Hadamard Transforms and inversion techniques to generate the possible minimum disparity values for the data to be encoded. A minimum disparity value is then selected that also provides sufficient transition density.

Claims

1. A data encoding apparatus comprising:

at least one disparity counter adaptable to calculate the disparity for a group of data bits; and

a Hadamard Transform connected to said disparity counter and adaptable to generate possible disparity values from said disparity calculation provided by said disparity counter, wherein a minimum disparity value for said group of data bits is determined.

2. The data encoding apparatus of claim 1, wherein said disparity counter further comprises determining whether sufficient transition density exists for said group of data bits, wherein said Hadamard Transform determines whether said disparity values have sufficient transition density by evaluating transition density data provided by said disparity counter.

3. The data encoding apparatus of claim 1, wherein said Hadamard Transform comprises a Fast Hadamard Transform.

4. The data encoding apparatus of claim 1, wherein said group of data bits comprises one or more nibbles.

5. The data encoding apparatus of claim 1, wherein additional data bits having zero disparity and sufficient transition density are combined with said group of data bits to provide a data frame corresponding to a power of two.

6. The data encoding apparatus of claim 1, wherein said Hadamard Transform can be expressed by the equation $h$

(k,n)=(-1)∑

i

 



ki

ni.

7. The data encoding apparatus of claim 1, wherein said disparity counter further provides least and most significant bits, of said group of data bits, which are used by said Hadamard Transform to determine if said disparity values have sufficient transition density.

8. The data encoding apparatus of claim 1, wherein said Hadamard Transform comprises a Fast Hadamard Transform comprised of at least one two-point Hadamard Transform.

9. The data encoding apparatus of claim 1, further comprising a minimum pattern selector connected to said Hadamard Transform and which selects the minimal disparity value, output by said Hadamard Transform, for said group of data bits.

10. The data encoding apparatus of claim 9, wherein said minimum pattern selector further comprises receiving disparity values for coding bits from a subsequent data encoder to combine with said minimal disparity values from said Hadamard Transform prior to selecting said minimal disparity value.

11. The data encoding apparatus of claim 9, further comprising an inversion vector generator connected to said minimum pattern selector and which generates the correct inversion pattern for the data output by said data encoding apparatus.

12. A method of encoding data, said method comprising:

receiving a group of data bits;

calculating the disparity for said group of data bits; and

generating possible disparity values from said disparity calculation by employing a Walsh-Hadamard Transform to determine a minimum disparity value for said group of data bits.

13. The method of claim 12, further comprising calculating transition density for said group of data bits, said Walsh-Hadamard Transform determining whether said disparity values have sufficient transition density by evaluating said calculated transition density.

14. The method of claim 12, wherein said generating step further comprises employing at least one Fast Hadamard Transform.

15. The method of claim 12, further comprising dividing said group of data bits into nibbles.

16. The method of claim 12, further comprising combining said group of data bits with additional data bits having zero disparity and sufficient transition density to provide a data frame corresponding to a power of two or three times a power of two.

17. The method of claim 12, further comprising providing least and most significant bits from said group of data bits, said Walsh-Hadamard Transform determining whether said disparity values have sufficient transition density by evaluating said least and most significant bits.

18. The method of claim 12, further comprising selecting an output from said Walsh-Hadamard Transform having minimum disparity value for said group of data bits.

19. The method of claim 12, further comprising receiving disparity values for coding bits from a subsequent data encoder to combine with said minimal disparity values from said Walsh-Hadamard Transform prior to selecting said minimal disparity value.

20. The method of claim 12, further comprising calculating an inversion pattern for an output from said Walsh-Hadamard Transform to encode said group of data bits.

21. A disparity and transition density control device comprising:

a disparity and transition density counter adapted to receive successive bytes of data and calculate the disparity for each said byte of data;

a shift register adapted to also receive said successive bytes of data;

a Fast Hadamard Transform coupled to said disparity and transition density counter and adapted to generate disparity values from said disparity calculations;

a minimum pattern selector coupled to said Fast Hadamard Transform and adapted to select the minimal disparity value from said disparity values generated by said Fast Hadamard Transform; and

an inversion vector generator coupled to said minimum pattern selector and adapted to generate the correct inversion pattern for said successive bytes of data output from said shift register.

22. The device of claim 21, wherein said Fast Hadamard Transform is further adapted to determine whether said disparity values have sufficient transition density by evaluating transition density data provided by said disparity and transition density counter.

23. The device of claim 21, wherein said Fast Hadamard Transform comprises a plurality of two-point Fast Hadamard transforms arranged in consecutive stages.

24. The device of claim 23, wherein each stage generates 2^{(stage number+1)} values which can be rearranged prior to providing the values to the following stage.