Content addressable magnetic random access memory

• US 6,304,477 B1
• Filed: 01/31/2001
• Issued: 10/16/2001
• Est. Priority Date: 01/31/2001
• Status: Expired due to Term

• Current Assignee: Everspin Technologies Incorporated
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Naji, Peter K.
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): Lam, David
• Application Number:
  US09/774,934
• Time in Patent Office: 258 Days
• Field of Search: 365/50, 365/158, 365/171, 365/173, 365/207, 365/55, 365/66
• US Class Current: 365/50
• CPC Class Codes: G11C 15/02 using magnetic elements
• CPC Class Codes: G11C 15/046 using non-volatile storage elements

Abstract

A content addressable magnetic random access memory cell including a differentially connected pair of MTJs and comparison and match detection circuitry connected to the MTJs and including differential tag bitlines, differential tag program bitlines, an enable line, a word line, a digit line, and a match line. The match line provides an indication of a match between input data placed on the differential tag bitlines and stored data in the cell.

Claims

1. A magnetic random access memory cell comprising:

a differentially connected pair of magnetic tunnel junctions; and

programming and detection circuitry connected to the differentially connected pair and including differential bitlines, differential program bitlines, an enable line, a word line, and a digit line.

2. A content addressable magnetic random access memory cell comprising:

a differentially connected pair of magnetic tunnel junctions; and

comparison and match detection circuitry connected to the differentially connected pair and including differential tag bitlines, differential tag program bitlines, an enable line, a word line, a digit line, and a match line, the match line providing an indication of a match between input data placed on the differential tag bitlines and stored data in the cell.

3. A content addressable magnetic random access memory cell as claimed in claim 2 wherein the differentially connected pair of magnetic tunnel junctions and the comparison and match detection circuitry are formed on a common supporting substrate.

4. A content addressable magnetic random access memory cell as claimed in claim 2 wherein the differentially connected pair of magnetic tunnel junctions form a nonvolatile memory.

5. A content addressable magnetic random access memory cell as claimed in claim 2 wherein the differential tag bitlines and the differential tag program bitlines include a tag bitline coupled to a first of the differentially connected pair of magnetic tunnel junctions, a tag bitline-not coupled to a second of the differentially connected pair of magnetic tunnel junctions, a tag program bitline connected to the first of the differentially connected pair of magnetic tunnel junctions, and a tag program bitline-not connected to the second of the differentially connected pair of magnetic tunnel junctions.

6. A content addressable magnetic random access memory cell comprising:

a first magnetic tunnel junction with a first side connected through a first series connected pair of transistors to a first junction and a second magnetic tunnel junction with a first side connected through a second series connected pair of transistors to a second junction, a second side of the first magnetic tunnel junction connected to a programming bitline and a second side of the second magnetic tunnel junction connected to a programming bitline-not, and a control terminal of a first of the first series connected pair of transistors connected to an enable line and a control terminal of a first of the second series connected pair of transistors connected to the enable line;

the first junction being coupled through a first transistor to a bitline with a control terminal of the first transistor being connected to a word line, and the second junction being coupled through a second transistor to a bitline-not with a control terminal of the second transistor being connected to the word line;

the first junction being coupled through a first enable transistor to a power input terminal with a control terminal of the first enable transistor connected to the enable line, and the second junction being coupled through a second enable transistor to the power input terminal with a control terminal of the second enable transistor connected to the enable line;

the first junction being coupled through a first differential transistor to the power input terminal with a control terminal of the first differential transistor connected to a control terminal of a second of the first series connected pair of transistors and to the second junction, and the second junction being coupled through a second differential transistor to the power input terminal with a control terminal of the second differential transistor connected to a control terminal of a second of the second series connected pair of transistors and to the first junction; and

a first series connected pair of match transistors connected between the power input terminal and a match line with a control terminal of a first of the first pair of match transistors connected to the bitline and a control terminal of a second of the first pair of match transistors connected to the second junction, and a second series connected pair of match transistors connected between the power input terminal and the match line with a control terminal of a first of the second pair of match transistors connected to the bitline-not and a control terminal of a second of the second pair of match transistors connected to the first junction.

7. A content addressable magnetic random access memory cell as claimed in claim 6 wherein the first and second series connected pairs of transistors, the first and second transistors, the first and second enable transistors, the first and second differential transistors, and the first and second pairs of match transistors are formed in a semiconductor substrate and the first and second magnetic tunnel junctions are formed in layers positioned on the semiconductor substrate.

8. A content addressable magnetic random access memory cell as claimed in claim 7 including in addition a digit line associated with the first and second magnetic tunnel junctions and positioned below the first and second magnetic tunnel junctions with the programming bitline being positioned above the first magnetic tunnel junction and the programming bitline-not being positioned above the second magnetic tunnel junction.

9. An array of memory cells connected to form a content addressable, nonvolatile memory comprising:

a plurality of memory cells arranged in rows and columns;

each memory cell including a differentially connected pair of magnetic tunnel junctions, and a tag bitline, a tag bitline-not, a tag program bitline, a tag program bitline-not, an enable line, a word line, a digit line, and a match line, the match line providing an indication of a match between input data placed on the differential tag bitlines and stored data in the cell;

the tag bitline, tag bitline-not, tag program bitline, tag program bitline-not, and enable line for each memory cell in a column being coupled to the tag bitline, tag bitline-not, tag program bitline, tag program bitline-not, and enable line for each other memory cell in the column, respectively;

the word line, digit line, and match line for each memory cell in a row being coupled to the word line, digit line, and match line for each other memory cell in the row; and

match detection circuitry coupled to the match lines in each row.

10. An array of memory cells connected to form a content addressable, nonvolatile memory as claimed in claim 9 wherein the differentially connected pair of magnetic tunnel junctions include a plurality of transistors formed in a semiconductor substrate with the magnetic tunnel junctions formed in layers disposed on the semiconductor substrate.

11. An array of memory cells connected to form a content addressable, nonvolatile memory as claimed in claim 10 wherein each row of memory cells includes the digit line positioned below and adjacent each memory cell in the row, each column of memory cells includes the programming bitline positioned adjacent and above a first magnetic tunnel junction of the differentially connected pair of magnetic tunnel junctions in each memory cell in the column, and each column of memory cells includes the programming bitline-not positioned adjacent and above a second magnetic tunnel junction of the differentially connected pair of magnetic tunnel junctions in each memory cell in the column.