Shielded bit line architecture for memory arrays

• US 6,304,479 B1
• Filed: 06/23/2000
• Issued: 10/16/2001
• Est. Priority Date: 06/23/2000
• Status: Expired due to Fees

• Current Assignee: Qimonda AG (Infineon Technologies AG), White Oak Semiconductor Partnership
• Original Assignee: Infineon Technologies North America Corporation (Infineon Technologies AG), Infineon Technologies Richmond LP (Infineon Technologies AG)
• Inventors: Fera, Michael, Vollrath, Joerg, Moore, Philip
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US09/602,758
• Time in Patent Office: 480 Days
• Field of Search: 365/63, 365/206, 365/190, 365/149, 365/154, 365/220
• US Class Current: 365/63
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/18 Bit line organisation; Bit line lay-out

Abstract

A memory array, in accordance with the invention, includes a plurality of memory cells disposed in an array. A plurality of bitlines are included for reading and writing data to and from the memory cells. The plurality of bitlines include a first group of bitlines and a second group of bitlines. Each bitline of the first group is interposed between bitlines of the second group, and each bitline of the second group is interposed between bitlines of the first group. The first group of bitlines are active when the second group of bitlines are inactive, and the second group of bitlines are active when the first group of bitlines are inactive such that adjacent inactive bitlines provide a shield to prevent cross-coupling between active bitlines.

Claims

1. A memory array comprising:

a plurality of memory cells;

a plurality of bitlines for reading and writing data to and from the memory cells, the plurality of bitlines including a first group of bitlines and a second group of bitlines, each bitline of the first group being interposed between bitlines of the second group and each bitline of the second group being interposed between bitlines of the first group;

at least one switch disposed along a length of each bitline to connect and disconnect the bitline to and from a sense amplifier to activate and deactivate the bitlines wherein the first group of bitlines are active when the second group of bitlines are inactive and the second group of bitlines are active when the first group of bitlines are inactive such that adjacent inactive bitlines provide a shield to prevent cross-coupling between active bitlines; and

a plurality of sense amplifiers, each sense amplifier being coupled to a bitline of the first group and a bitline of the second group on a first side of each sense amplifier, and each sense amplifier being coupled to a bitline of the first group and a bitline of the second group on a second side of each sense amplifier.

2. The memory array as recited in claim 1, further comprising dummy lines disposed in the array for balancing capacitance in the plurality of sense amplifiers.

3. The memory array as recited in claim 1, wherein the switches include field effect transistors.

4. The memory array as recited in claim 1, wherein the switches include first switches associated with the first group of bitlines and second switches associated with the second group of bitlines, the first switches being switched by a first signal line and the second switches being switched by a second signal line.

5. The memory array as recited in claim 1, wherein the memory array includes a folded bitline architecture.

6. The memory array as recited in claim 1, wherein the inactive bitlines include a floating potential.

7. An memory array comprising:

a plurality of memory cells disposed in an array;

a plurality of wordlines extending through the array to enable access to the memory cells when the wordlines are enabled;

a plurality of bitlines for reading and writing data to and from the memory cells when the wordlines are enabled, the plurality of bitlines including a first group of bitlines and a second group of bitlines, each bitline of the first group being interposed between bitlines of the second group and each bitline of the second group being interposed between bitlines of the first group; and

a plurality of sense amplifiers, each sense amplifier being coupled to a bitline of the first group and a bitline of the second group on a first side of each sense amplifier, and each sense amplifier being coupled to a bitline of the first group and a bitline of the second group on a second side of each sense amplifier,

the first group of bitlines being active when the second group of bitlines are inactive and the second group of bitlines being active when the first group of bitlines are inactive such that adjacent inactive bitlines provide a shield to prevent cross-coupling between active bitlines.

8. The memory array as recited in claim 7, further comprising dummy lines disposed at an end of the array for balancing capacitance in the plurality of sense amplifiers.

9. The memory array as recited in claim 7, wherein the plurality bitlines include switches to activate and deactivate the plurality of bitlines.

10. The memory array as recited in claim 9, wherein the switches include field effect transistors.

11. The memory array as recited in claim 9, wherein the switches include first switches associated with the first group of bitlines and second switches associated with the second group of bitlines, the first switches being switched by a first signal line and the second switches being switched by a second signal line.

12. The memory array as recited in claim 7, wherein the memory array includes a folded bitline architecture.

13. The memory array as recited in claim 7, wherein the inactive bitlines include a floating potential.

14. An architecture for bitlines for memory arrays comprising:

a plurality of memory cells disposed in an array;

a plurality of wordlines extending through the array to enable access to the memory cells when the wordlines are enabled;

a plurality of bitlines for reading and writing data to and from the memory cells when the wordlines are enabled, the plurality of bitlines including;

a first group of bitlines and a second group of bitlines, each bitline of the first group being interposed between bitlines of the second group and each bitline of the second group being interposed between bitlines of the first group; and

each of the plurality of bitlines including a switch for activating and deactivating each bitline; and

a plurality of sense amplifiers, each sense amplifier being coupled to a bitline of the first group and a bitline of the second group on a first side of each sense amplifier, and each sense amplifier being coupled to a bitline of the first group and a bitline of the second group on a second side of each sense amplifier,

the first group of bitlines being active when the second group of bitlines are inactive and the second group of bitlines being active when the first group of bitlines are inactive such that adjacent inactive bitlines provide a shield to prevent cross-coupling between active bitlines.

15. The architecture as recited in claim 14, further comprising dummy lines, disposed at an end of the array, for balancing capacitance in the plurality of sense amplifiers.

16. The architecture as recited in claim 14, wherein the switches include first switches associated with the first group of bitlines and second switches associated with the second group of bitlines, the first switches being switched by a first signal line and the second switches being switched by a second signal line.

17. The architecture as recited in claim 14, wherein the architecture includes a folded bitline architecture.

18. The architecture as recited in claim 14, wherein the switches include field effect transistors.

19. The architecture as recited in claim 14, wherein the inactive bitlines include a floating potential.