Sensing time control device and method

• US 6,304,486 B1
• Filed: 12/20/1999
• Issued: 10/16/2001
• Est. Priority Date: 12/20/1999
• Status: Expired due to Term

• Current Assignee: Socionext Inc.
• Original Assignee: Fujitsu Limited
• Inventors: Yano, Masaru
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US09/468,422
• Time in Patent Office: 666 Days
• Field of Search: 365/185.22, 365/185.2, 365/185.21, 365/185.11, 365/185.12
• US Class Current: 365/185.22
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

A NAND type flash memory device has a reference bit line and a reference page buffer to control sensing time during program and erase verification operations. Each reference memory cell in the reference bit line is pre-programmed with a reference bit. A set initiation signal triggers detection and latching of the reference bit by the reference page buffer. When the reference bit is latched, an output of the reference page buffer is used as a set signal to trigger the program and erase verification operations of corresponding memory cells.

Claims

1. A method of performing a program verification operation comprising:

programming a reference memory cell, the reference memory cell corresponding to a page in a memory cell block of a NAND type flash memory, the memory cell block comprising a plurality of pages, and one reference memory cell being provided for each page;

programming a memory cell on the same page as the programmed reference memory cell;

generating a set signal using a content of the reference memory cell; and

using the set signal to initiate the program verification operation for the memory cell.

2. The method of performing a program verification operation of claim 1 wherein the programmed reference memory cell is programmed to a negatively charged state.

3. The method of performing a program verification operation of claim 1 wherein the programmed reference memory cell is programmed to regular programming state.

4. The method of performing a program verification operation of claim 1 wherein a reference page buffer is coupled to the programmed reference memory cell and a data page buffer is coupled to the memory cell, the reference page buffer is used to read and store a content of the reference memory cell and the data page buffer is used to read and store a content of the programmed memory cell.

5. The method of performing a program verification operation of claim 4 wherein generating the set signal with the content of the programmed reference memory cell comprises providing a set initiation signal to the reference page buffer to store the content of the programmed reference memory cell as a content of the reference page buffer and outputting the content of the reference page buffer as the set signal.

6. The method of performing a program verification operation of claim 4 wherein using the set signal to initiate the program verification operation of the memory cell comprises providing the set signal to the data page buffer to store the content of the memory cell as a content of the data page buffer.

7. The method of performing a program verification operation of claim 6 further comprising comparing the content of the data page buffer with a corresponding content of an I/O register and buffer.

8. The method of performing a program verification operation of claim 7 further comprising re-programming the memory cell, re-generating the set signal with the content of the programmed reference memory cell and using the set signal to initiate another program verification operation of the memory cell, when the content of the data page buffer does not match the corresponding content of the I/O register and buffer.

9. The method of performing a program verification operation of claim 1 further comprising programming a plurality of memory cells on the same page as the programmed reference memory cell;

and using the set signal to initiate the program verification operation for the plurality of memory cells.

10. The method of performing a program verification operation of claim 9 wherein the programmed reference memory cell is programmed to a negatively charged state.

11. The method of performing a program verification operation of claim 9 wherein the programmed reference memory cell is coupled to a reference page buffer and each of the plurality of memory cells is coupled to a corresponding one of a plurality of data page buffers, the reference page buffer is used to read and store a content of the programmed reference memory cell and each of the plurality of data page buffers is used to read and store a content of the corresponding one of the plurality of memory cells.

12. The method of performing a program verification operation of claim 11 wherein generating the set signal with the content of the programmed reference memory cell comprises providing a set initiation signal to the reference page buffer to store the content of the programmed reference memory cell as a content of the reference page buffer and outputting the content of the reference page buffer as the set signal.

13. The method of performing a program verification operation of claim 11 wherein using the set signal to initiate the program verification operation of the plurality of memory cells comprises providing the set signal to each of the plurality of data page buffers to store the content of the corresponding one of the plurality of memory cells as a content of each of the plurality of data page buffers.

14. The method of performing a program verification operation of claim 13 further comprising comparing the contents of the plurality of data page buffers with corresponding contents of an I/O register and buffer.

15. The method of performing a program verification operation of claim 14 further comprising re-programming the plurality of memory cells, re-generating the set signal with the content of the programmed reference memory cell and using the set signal to initiate another program verification operation of the plurality of memory cells, when at least one of the contents of the plurality of data page buffers does not match the corresponding content of the I/O register and buffer.

16. A method of performing an erase verification operation comprising:

programming a reference memory cell, the reference memory cell corresponding to a page in a memory cell block of a NAND type flash memory, the memory cell block comprising a plurality of pages, and one reference memory cell being provided for each page;

erasing a memory cell on the same page as the programmed reference memory cell;

generating a set signal using a content of the reference memory cell; and

using the set signal to initiate the erase verification operation for the memory cell.

17. The method of performing an erase verification operation of claim 16 wherein the programmed reference memory cell is programmed to a negatively charged state.

18. The method of performing an erase verification operation of claim 16 wherein a reference page buffer is coupled to the programmed reference memory cell and a data page buffer is coupled to the memory cell, the reference page buffer is used to read and store a content of the programmed reference memory cell and the data page buffer is used to read and store a content of the memory cell.

19. The method of performing an erase verification operation of claim 18 wherein generating the set signal with the content of the programmed reference memory cell comprises providing a set initiation signal to the reference page buffer to store the content of the programmed reference memory cell as a content of the reference page buffer and outputting the content of the reference page buffer as the set signal.

20. The method of performing an erase verification operation of claim 18 wherein using the set signal to initiate the erase verification operation of the memory cell comprises providing the set signal to the data page buffer to store the content of the memory cell as a content of the data page buffer.

21. The method of performing an erase verification operation of claim 20 further comprising checking the content of the data page buffer to determine whether or not the memory cell is in a discharged state.

22. The method of performing an erase verification operation of claim 21 further comprising re-erasing the memory cell, re-generating the set signal with the content of the programmed reference memory cell and using the set signal to initiate another erase verification operation of the memory cell, when the content of the data page buffer indicates that the memory cell is in a negatively charged state.

23. The method of performing an erase verification operation of claim 16 further comprising erasing a plurality of memory cells on the same page as the programmed reference memory cell;

and using the set signal to initiate the erase verification operation for the plurality of memory cells.

24. The method of performing an erase verification operation of claim 23 wherein the programmed reference memory cell is programmed to a negatively charged state.

25. The method of performing an erase verification operation of claim 23 wherein the programmed reference memory cell is coupled to a reference page buffer and each of the plurality of memory cells is coupled to a corresponding one of a plurality of data page buffers, the reference page buffer is used to read and store a content of the programmed reference memory cell and each of the plurality of data page buffers is used to read and store a content of the corresponding one of the plurality of memory cells.

26. The method of performing an erase verification operation of claim 25 wherein generating the set signal with the content of the reference memory cell comprises providing a set initiation signal to the reference page buffer to store the content of the programmed reference memory cell as a content of the reference page buffer and outputting the content of the reference page buffer as the set signal.

27. The method of performing an erase verification operation of claim 25 wherein using the set signal to initiate the erase verification operation of the plurality of memory cells comprises providing the set signal to each of the plurality of data page buffers to store the content of the corresponding one of the plurality of memory cells as a content of each of the plurality of data page buffers.

28. The method of performing an erase verification operation of claim 27 further comprising checking the content of each of the plurality of data page buffers to determine whether or not the corresponding one of the plurality of memory cells is in a discharged state.

29. The method of performing an erase verification operation of claim 28 further comprising re-erasing the plurality of memory cells, re-generating the set signal with the content of the programmed reference memory cell and using the set signal to initiate another erase verification operation of the plurality of memory cells, when the contents of the plurality of data page buffers indicate that at least one of the plurality of memory cells is in a negatively charged state.

30. A method of verifying a content of a memory cell in a memory cell block of a NAND type flash memory, the memory cell block comprising a plurality of pages, and one reference memory cell being provided for each page comprising:

programming a reference memory cell on the same page of the memory cell block in the NAND type flash memory as the memory cell;

sensing a content of the programmed reference memory cell; and

verifying the content of the memory cell when the content of the programmed reference memory cell has been sensed.

31. A method of providing a set signal to a page buffer associated with a memory cell in a memory cell block of a NAND type flash memory, the memory cell block comprising a plurality of pages, and one reference memory cell being provided for each page, the method comprising:

programming a reference memory cell coupled to a reference page buffer, the programmed reference memory cell being in the same page of the memory cell block in the NAND type flash memory as the memory cell;

setting a voltage of a node in the reference page buffer based on the content of the programmed reference memory cell;

and providing the voltage at the node to the page buffer as the set signal.

32. The method of providing a set signal to a page buffer associated with a memory cell of claim 31 further comprising:

presetting the voltage at the node to a logic high,

wherein the step of setting the voltage of the node comprises setting the voltage at the node to a logic low.

33. The method of providing a set signal to a page buffer associated with a memory cell of claim 31 wherein the step of providing the voltage at the node to the page buffer as the set signal comprises the steps of inverting the voltage at the node and providing the inverted voltage to the page buffer as the set signal.

34. A sensing time control circuit for use in NAND type flash memory, the sensing time control circuit comprising:

a reference page buffer which receives a set initiation signal and generates a set signal using a content of one reference memory cell provided for a page of a memory cell block in the NAND type flash memory; and

a plurality of data page buffers that receive the set signal and store contents of a plurality of memory cells in the same page as the one reference memory cell, each of the plurality of data page buffers storing a content of an associated one of the plurality of memory cells.

35. The sensing time control circuit of claim 34 wherein the reference page buffer comprises a set initiation transistor receiving the set initiation signal and turning on upon receiving the set initiation signal and a latch coupled to the set initiation transistor, the latch providing the set signal.

36. The sensing time control circuit of claim 34 wherein each of the plurality of reference page buffers comprises a set transistor receiving the set signal and turning on upon receiving the set signal and a latch coupled to the set transistor, the latch providing a content to an associated memory cell.