Method of operation of a memory controller

• US 6,304,937 B1
• Filed: 09/25/2000
• Issued: 10/16/2001
• Est. Priority Date: 04/18/1990
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Horowitz, Mark, Farmwald, Michael
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US09/669,295
• Time in Patent Office: 386 Days
• Field of Search: 710/35, 710/129, 710/100, 365/233, 365/235, 365/238.5, 713/400, 713/500, 713/502, 713/600
• US Class Current: 710/310
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0215 with look ahead addressing means
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 12/0684 with feedback, e.g. presence or absence of unit detected by addressing, overflow detection
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/161 with latency improvement
• CPC Class Codes: G06F 13/1678 using bus width
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/376 using a contention resolving method, e.g. collision detection, collision avoidance
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 2207/108 Wide data ports
• CPC Class Codes: G11C 29/88 with partially good memories
• CPC Class Codes: G11C 5/00 Details of stores covered by group G11C11/00
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 5/06 Arrangements for interconnecting storage elements electrically, e.g. by wiring
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 5/066 : Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/1006 : Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1012 : Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
• CPC Class Codes: G11C 7/1045 : Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1057 : Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 : Output synchronization
• CPC Class Codes: G11C 7/1069 : I/O lines read out arrangements
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1084 : Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/225 : Clock input buffers
• CPC Class Codes: G11C 8/00 : Arrangements for selecting an address in a digital store for stores using transistors G11C11/407, G11C11/413
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method of operation of a memory controller device, the method of operation comprises issuing a write request to a memory device synchronously with respect to an external clock signal, wherein in response to the write request, a memory device inputs first and second portions of data. The method of operation further includes outputting the first portion of data synchronously with respect to a first edge transition of an external clock signal; and outputting the second portion of data from the bus synchronously with respect to a second edge transition of the external clock signal. The first and second edge transitions of the external clock signal are of transitions of the same clock cycle.

Claims

1. A method of controlling a synchronous memory device, wherein the memory device includes a plurality of memory cells, the method of controlling the memory device comprises:

issuing a first operation code to the memory device, wherein in response to the first operation code, the memory device outputs first and second portions of data;

sampling the first portion of data synchronously with respect to a rising edge transition of an external clock signal; and

sampling the second portion of data synchronously with respect to a falling edge transition of the external clock signal.

2. The method of claim 1 further including:

providing block size information to the memory device, wherein the block size information defines an amount of data to be output by the memory device.

3. The method of claim 1 wherein, in response to the first operation code, the first portion of data is output after a programmed amount of time transpires.

4. The method of claim 1 further including:

providing access time information to the memory device; and

issuing a second operation code, wherein in response to the second operation code, the memory device stores the access time information in a register within the memory device.

5. The method of claim 4 wherein the access time information is representative of a number of clock cycles of the external clock signal to transpire before the first portion of data is output by the memory device in response to the first operation code.

6. The method of claim 4 wherein the access time information is representative of a number of clock cycles of the external clock signal to transpire before the second portion of data is output by the memory device.

7. The method of claim 1 wherein both the rising and falling edge transitions of the external clock signal include voltage swings of less than one volt.

8. The method of claim 1 further including providing address information to the memory device synchronously with respect to the external clock signal.

9. The method of claim 8 wherein the address information is provided synchronously with respect to rising and falling edges of the external clock signal.

10. The method of claim 8 wherein the address information and the first operation code are provided in a request packet.

11. The method of claim 10 wherein the address information and the first operation code are provided in the same request packet.

12. The method of claim 8 wherein the address information and the first operation code are output onto an external bus, wherein the external bus includes a set of signal lines to multiplex data control information, and address information.

13. The method of claim 1 wherein the rising edge transition of the external clock signal and the falling edge transition of the external clock signal transpire in the same clock cycle of the external clock signal.

14. The method of claim 1 wherein the first operation code is issued synchronously with respect to the external clock signal.

15. The method of claim 14 wherein the first operation code is output onto an external bus.

16. The method of claim 15 wherein the external bus includes a set of signal lines to multiplex data, control information, and address information.

17. The method of claim 1 wherein the first operation code includes precharge information.

18. A controller device for controlling a synchronous memory device, the controller device comprising:

output driver circuitry to provide an operation code to the memory device, wherein in response to the operation code, the memory device outputs a first portion of data synchronously with respect to a rising edge transition of an external clock signal and a second portion of data synchronously with respect to a falling edge transition of the external clock signal; and

input receiver circuitry to sample the first portion of data and the second portion of data output by the memory device.

19. The controller device of claim 18 wherein the input receiver circuitry includes first latch circuitry to latch the first portion of data, and second latch circuitry to latch the second portion of data.

20. The controller device of claim 18 further including a delay lock loop circuit, coupled to the external clock signal, to generate a first internal clock signal, wherein the input receiver circuitry samples the first portion of data in response to the first internal clock signal.

21. The controller device of claim 20 wherein the delay lock loop circuit generates a second internal clock signal that is complementary to the first internal clock signal, wherein the input receiver circuitry samples the second portion of data in response to the second internal clock signal.

22. The controller device of claim 18 wherein both the rising and falling edge transitions of the external clock signal include voltage swings of less than one volt.

23. The controller device of claim 18 wherein the input receiver circuitry samples an amount of data output by the memory device in response to the operation code wherein the amount of data is sampled during a plurality of clock cycles of the external clock signal.

24. The controller device of claim 23 wherein the output driver circuitry provides block size information to the memory device, wherein the block size information is representative of the amount of data output by the memory device in response to the operation code, and wherein, in response to the operation code, the memory device outputs the amount of data during a plurality of clock cycles of the external clock signal.

25. The controller device of claim 24 wherein the operation code and the block size information are included in a request packet.

26. The controller device of claim 18 wherein the input receiver circuitry samples the first portion of data from an external bus.

27. The controller device of claim 26 wherein the external bus includes a set of signal lines to transmit multiplexed address information, data and control information.

28. The controller device of claim 18 wherein the output driver circuitry and the input receiver circuitry are connected to a common pad.

29. The controller device of claim 18 wherein the output driver circuitry provides the operation code synchronously with respect to the external clock signal.

30. A method of operation of a memory controller device, the method comprises:

issuing an operation code to a memory device synchronously with respect to an external clock signal, wherein the operation code instructs the memory device to input first and second portions of data;

outputting the first portion of data synchronously with respect to a rising edge transition of the external clock signal; and

outputting the second portion of data synchronously with respect to a falling edge transition of the external clock signal.

31. The method of claim 30 wherein the controller device outputs the first portion of data after a delay time transpires.

32. The method of claim 30 further including providing to the memory device information that represents an amount of time which lapses before data is input by the memory device.

33. The method of claim 32 wherein the information is provided in the form of a value and wherein the value is representative of a number of clock cycles of the external clock signal.

34. The method of claim 30 wherein the first and second edge transitions of the external clock signal include voltage swings of less than one volt.

35. The method of claim 30 wherein the first portion of data and second portion of data include voltage swings of less than one volt.

36. The method of claim 30 further including providing address information to the memory device synchronously with respect to the external clock signal.

37. The method of claim 30 further includin g providing block size information to the memory device, wherein the block size information is representative of an amount of data to be input by the memory device in response to the operation code.

38. The method of claim 37 further including outputting the amount of data to the memory device during a plurality of clock cycles of the external clock signal.

39. The method of claim 38 further including providing address information to the memory device synchronously with respect to the rising and falling edges of the external clock signal.

40. The method of claim 39 wherein the block size information, the address information and the operation code are included in a write request packet.