Hardware access control locking

• US 6,304,970 B1
• Filed: 09/02/1997
• Issued: 10/16/2001
• Est. Priority Date: 09/02/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Weingart, Steve Harris, Bizzaro, Mario, Kravitz, Jeffrey Kenneth, Pedrina, Gianluca, Lindemann, Mark John, Hack, Michel Henri Theodore, Condorelli, Vincenzo, Smith, Sean William, Palmer, Elaine Rivette
• Primary Examiner(s): Barron, Jr., Gilberto
• Assistant Examiner(s): Revak, Christopher A.
• Application Number:
  US08/922,792
• Time in Patent Office: 1,505 Days
• Field of Search: 713/200, 713/201, 711/163, 714/39, 714/49, 714/50, 710/200, 709/100, 709/104, 709/108, 709/225, 709/226, 709/229
• US Class Current: 726/2
• CPC Class Codes: G06F 21/57 Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
• CPC Class Codes: G06F 21/74 operating in dual or compartmented mode, i.e. at least one secure mode
• CPC Class Codes: G06F 2221/2105 Dual mode as a secondary aspect

Abstract

An apparatus for permitting access to protected code, protected data or protected devices only when a computer system is in a trusted state, where said trusted state occurs only when said system is executing trusted code under a set of preselected conditions. This apparatus also has a device for exiting the trusted state and for preventing access to protected code, data and devices when the trusted state is exited. The computer system is also programmed to automatically generate a disabling signal upon the completion of execution of trusted code, and this disabling signal will result in the prevention of access to protected devices or code.

Claims

1. An apparatus for protecting access to control code, data, and devices in a computer system, said apparatus comprising:

a. means for generating a disabling signal upon completion of execution by said computer system of trusted code;

b. a state machine for determining when said computer system is in any of a number of trusted states, each trusted state being defined as a state in which said computer is executing trusted code in a correct context, said correct context being that the trusted code has been entered under a set of preselected conditions of operation of said processor, and wherein said state machine has an input for receiving said disabling signal and wherein said state machine determines that said computer system is no longer in any of said trusted states upon receiving said disabling signal;

c. means for allowing access by said system to said control code, data and devices when said state machine determines that said system is in one of said trusted states; and

d. means for preventing access to said control code, data and devices when said computer system exits any one of said trusted states.

2. An apparatus as recited in claim 1, wherein said state machine is a microprocessor.

3. An apparatus as recited in claim 1, wherein said state machine is a flip-flop circuit.

4. An apparatus as recited in claim 1, wherein said state machine has reset signal as its input, where the reset signal causes the processor to start the execution of trusted code.

5. An apparatus as recited in claim 1, wherein said state machine generates an output signal in response to said disabling signal to prevent access to either said control code, said data or said devices.

6. An apparatus as recited in claim 1, wherein said state machine has an input for entering a secret key wherein said state machine will generate said output signal to prevent access to said control code, data or said devices if said secret key is not entered in latter said input of said state machine.

7. An apparatus as recited in claim 1, wherein said means for allowing and preventing access by said system to said control code, said data and said devices comprises an AND gate for receiving a control signal from said processor and an output signal from said state machine, wherein an enable signal is generated when said output signal and said control signal are active, and wherein said enable signal permits access to said control code, said data, and said devices.

8. An method for protecting access to control code, data, and devices in a computer system, said method comprising the steps of:

a. generating a disabling signal upon completion of execution by said computer system of trusted code;

b. determining when said computer system is in any of a number of trusted states, each trusted state being defined as a state in which said computer is executing trusted code in a correct context, said correct context being that the trusted code has been entered under a set of preselected conditions of operation of said processor, and wherein said state machine has an input for receiving said disabling signal and wherein said state machine determines that said computer system is no longer in any of said trusted states upon receiving said disabling signal;

c. allowing access by said system to said control code, data and devices when said state machine determines that said system is in one of said trusted states; and

d. preventing access to said control code, data and devices when said computer system exits any one of said trusted states.